Ramesh Harjani

Ramesh Harjani

University of Minnesota-Twin Cities

H-index: 43

North America-United States

About Ramesh Harjani

Ramesh Harjani, With an exceptional h-index of 43 and a recent h-index of 20 (since 2020), a distinguished researcher at University of Minnesota-Twin Cities, specializes in the field of Analog Circuits for Communications.

His recent articles reflect a diverse array of research interests and contributions to the field:

Reinforcing the Connection between Analog Design and EDA

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs

A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts

Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN

AuxcellGen: A framework for autonomous generation of analog and memory unit cells

Minimum unit capacitance calculation for binary-weighted capacitor arrays

Ramesh Harjani Information

University

Position

E. F. Johnson Professor Electrical & Computer Engineering

Citations(all)

6714

Citations(since 2020)

1613

Cited By

5659

hIndex(all)

43

hIndex(since 2020)

20

i10Index(all)

136

i10Index(since 2020)

45

Email

University Profile Page

Google Scholar

Ramesh Harjani Skills & Research Interests

Analog Circuits for Communications

Top articles of Ramesh Harjani

Reinforcing the Connection between Analog Design and EDA

2024/1/22

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints

2024/1/22

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology

2023/9/11

MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs

2023/9/10

A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts

ACM Transactions on Design Automation of Electronic Systems

2023/9/9

Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN

2023/6/11

Jitesh Poojary
Jitesh Poojary

H-Index: 2

Ramesh Harjani
Ramesh Harjani

H-Index: 19

AuxcellGen: A framework for autonomous generation of analog and memory unit cells

2023/4/17

Minimum unit capacitance calculation for binary-weighted capacitor arrays

2023/4/17

Ramesh Harjani
Ramesh Harjani

H-Index: 19

An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

Microelectronics Reliability

2023/3/1

Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2023/1/23

GNN-based hierarchical annotation for analog circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2023/1/11

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps.

2022/4/13

Constructive common-centroid placement and routing for binary-weighted capacitor arrays

2022/3/14

A charge flow formulation for guiding analog/mixed-signal placement

2022/3/14

Are analytical techniques worthwhile for analog IC placement?

2022/3/14

Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

2022/1/21

Common-centroid layout for active and passive devices: A review and the road ahead

2022/1/17

Meghna Madhusudan
Meghna Madhusudan

H-Index: 5

Ramesh Harjani
Ramesh Harjani

H-Index: 19

Performance-driven wire sizing for analog integrated circuits

ACM Transactions on Design Automation of Electronic Systems

2022/12/24

DC-DC Power Converter Designs

2022/9/1

Ramesh Harjani
Ramesh Harjani

H-Index: 19

See List of Professors in Ramesh Harjani University(University of Minnesota-Twin Cities)

Co-Authors

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