Sachin Sapatnekar
University of Minnesota-Twin Cities
H-index: 67
North America-United States
Top articles of Sachin Sapatnekar
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Reinforcing the Connection between Analog Design and EDA | Kishor Kunal Meghna Madhusudan Jitesh Poojary S Ramprasath Arvind K Sharma | 2024/1/22 | |
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints | Kishor Kunal Jitesh Poojary S Ramprasath Ramesh Harjani Sachin S Sapatnekar | 2024/1/22 | |
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization | Ulya Karpuzcu Hüsrev Cılasun William Moy Ziqing Zeng Tahmida Islam | 2024/4/24 | |
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI | Chetan Choppali Sudarshan Nikhil Matkar Sarma Vrudhula Sachin S Sapatnekar Vidya A Chhabria | 2024/3/2 | |
2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices | Shiyu Guo Sachin Sapatnekar Jie Gu | 2024/2/18 | |
IR-Aware ECO Timing Optimization Using Reinforcement Learning | arXiv preprint arXiv:2402.07781 | Vidya A Chhabria Wenjing Jiang Sachin S Sapatnekar | 2024/2/12 |
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems | arXiv preprint arXiv:2306.09434 | Vidya A Chhabria Chetan Choppali Sudarshan Sarma Vrudhula Sachin S Sapatnekar | 2023/6/15 |
A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts | ACM Transactions on Design Automation of Electronic Systems | Ramprasath Srinivasa Gopalakrishnan Meghna Madhusudan Arvind K Sharma Jitesh Poojary Soner Yaldiz | 2023/9/9 |
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory | Mohammad Abdullah Al Shohel Vidya A Chhabria Nestor Evmorfopoulos Sachin S Sapatnekar | 2023/10/28 | |
A 48-node all-to-all connected coupled ring oscillator ising solver chip | Hao Lo William Moy Hanzhao Yu Sachin Sapatnekar Chris H Kim | 2023/1/20 | |
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design | Vidya A Chhabria Sachin S Sapatnekar | 2023/4/5 | |
Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN | Jitesh Poojary S Ramprasath Sachin S Sapatnekar Ramesh Harjani | 2023/6/11 | |
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators | arXiv preprint arXiv:2308.12120 | Hadi Esmaeilzadeh Soroush Ghodrati Andrew B Kahng Joon Kyung Kim Sean Kinzer | 2023/8/23 |
An Ising solver chip based on coupled ring oscillators with a 48-node all-to-all connected array architecture | Nature Electronics | Hao Lo William Moy Hanzhao Yu Sachin Sapatnekar Chris H Kim | 2023/10 |
Reusing GEMM hardware for efficient execution of depthwise separable convolution on ASIC-based DNN accelerators | Susmita Dey Manasi Suvadeep Banerjee Abhijit Davare Anton A Sorokin Steven M Burns | 2023/1/16 | |
The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues | Sachin S Sapatnekar | 2023/3/26 | |
AuxcellGen: A framework for autonomous generation of analog and memory unit cells | Sumanth Kamineni Arvind Sharma Ramesh Harjani Sachin S Sapatnekar Benton H Calhoun | 2023/4/17 | |
A Multicore GNN Training Accelerator | Sudipta Mondal S Ramprasath Ziqing Zeng Kishor Kunal Sachin S Sapatnekar | 2023/8/7 | |
3SAT on an All-to-All-Connected CMOS Ising Solver Chip | arXiv preprint arXiv:2309.11017 | Hüsrev Cılasun Ziqing Zeng Abhimanyu Kumar Hao Lo William Cho | 2023/9/20 |
Experimental demonstration of magnetic tunnel junction-based computational random-access memory | arXiv preprint arXiv:2312.14264 | Yang Lv Brandon R Zink Robert P Bloom Hüsrev Cılasun Pravin Khanal | 2023/12/21 |
