Arvind Sharma
University of Minnesota-Twin Cities
H-index: 11
North America-United States
Top articles of Arvind Sharma
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Reinforcing the Connection between Analog Design and EDA | Kishor Kunal Meghna Madhusudan Jitesh Poojary S Ramprasath Arvind K Sharma | 2024/1/22 | |
AuxcellGen: A framework for autonomous generation of analog and memory unit cells | Sumanth Kamineni Arvind Sharma Ramesh Harjani Sachin S Sapatnekar Benton H Calhoun | 2023/4/17 | |
Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Nibedita Karmokar Arvind K Sharma Jitesh Poojary Meghna Madhusudan Ramesh Harjani | 2023/1/23 |
Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF | Solid-State Electronics | Lomash Chandra Acharya Khoirom Johnson Singh Neha Gupta Mahipal Dargupally Neeraj Mishra | 2023/12/1 |
GNN-based hierarchical annotation for analog circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Kishor Kunal Tonmoy Dhar Meghna Madhusudan Jitesh Poojary Arvind K Sharma | 2023/1/11 |
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology | Meghna Madhusudan Jitesh Poojary Arvind K Sharma S Ramprasath Kishor Kunal | 2023/9/11 | |
A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts | ACM Transactions on Design Automation of Electronic Systems | Ramprasath Srinivasa Gopalakrishnan Meghna Madhusudan Arvind K Sharma Jitesh Poojary Soner Yaldiz | 2023/9/9 |
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure | Lomash Chandra Acharya Anubhav Kumar Khoirom Johnson Singh Neha Gupta Nayakanti Sai Shabarish | 2023/7/3 | |
Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs | Semiconductor Science and Technology | Sarita Yadav Nitanshu Chauhan Raghav Chawla Arvind Sharma Shashank Banchhor | 2022/7/12 |
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. | S Ramprasath Meghna Madhusudan Arvind K Sharma Jitesh Poojary Soner Yaldiz | 2022/4/13 | |
Constructive common-centroid placement and routing for binary-weighted capacitor arrays | Nibedita Karmokar Arvind K Sharma Jitesh Poojary Meghna Madhusudan Ramesh Harjani | 2022/3/14 | |
Performance-driven wire sizing for analog integrated circuits | ACM Transactions on Design Automation of Electronic Systems | Yaguang Li Yishuang Lin Meghna Madhusudan Arvind Sharma Sachin Sapatnekar | 2022/12/24 |
Common-centroid layout for active and passive devices: A review and the road ahead | Nibedita Karmokar Meghna Madhusudan Arvind K Sharma Ramesh Harjani Mark Po-Hung Lin | 2022/1/17 | |
Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Lomash Chandra Acharya Arvind Kumar Sharma Neeraj Mishra Khoirom Johnson Singh Mahipal Dargupally | 2022/12/21 |
Machine Learning for Analog Layout | Steven M Burns Hao Chen Tonmoy Dhar Ramesh Harjani Jiang Hu | 2022/8/10 | |
Variation aware timing model of CMOS inverter for an efficient ECSM characterization | Lomash Chandra Acharya Arvind kumar Sharma Venkatraman Ramakrishan Ajoy Mandal Sudeb Dasgupta | 2021/4/7 | |
Performance-aware common-centroid placement and routing of transistor arrays in analog circuits | Arvind K Sharma Meghna Madhusudan Steven M Burns Soner Yaldiz Parijat Mukherjee | 2021/11/1 | |
Machine Learning Techniques in Analog Layout Automation | Tonmoy Dhar Kishor Kunal Yaguang Li Yishuang Lin Meghna Madhusudan | 2021/3/22 | |
From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning | Juzheng Liu Shiyu Su Meghna Madhusudan Mohsen Hassanpourghadi Samuel Saunders | 2021/11/1 | |
A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET | Semiconductor Science and Technology | Sarita Yadav Nitanshu Chauhan Shobhit Tyagi Arvind Sharma Shashank Banchhor | 2021/10/25 |
Co-Authors
