Ramesh Harjani
University of Minnesota-Twin Cities
H-index: 43
North America-United States
Top articles of Ramesh Harjani
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Reinforcing the Connection between Analog Design and EDA | Kishor Kunal Meghna Madhusudan Jitesh Poojary S Ramprasath Arvind K Sharma | 2024/1/22 | |
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints | Kishor Kunal Jitesh Poojary S Ramprasath Ramesh Harjani Sachin S Sapatnekar | 2024/1/22 | |
An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer | Microelectronics Reliability | Tonmoy Dhar Jitesh Poojary Ramesh Harjani Sachin S Sapatnekar | 2023/3/1 |
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs | Yishuang Lin Yaguang Li Meghna Madhusudan Sachin S Sapatnekar Ramesh Harjani | 2023/9/10 | |
Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Nibedita Karmokar Arvind K Sharma Jitesh Poojary Meghna Madhusudan Ramesh Harjani | 2023/1/23 |
A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts | ACM Transactions on Design Automation of Electronic Systems | Ramprasath Srinivasa Gopalakrishnan Meghna Madhusudan Arvind K Sharma Jitesh Poojary Soner Yaldiz | 2023/9/9 |
GNN-based hierarchical annotation for analog circuits | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Kishor Kunal Tonmoy Dhar Meghna Madhusudan Jitesh Poojary Arvind K Sharma | 2023/1/11 |
Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN | Jitesh Poojary S Ramprasath Sachin S Sapatnekar Ramesh Harjani | 2023/6/11 | |
AuxcellGen: A framework for autonomous generation of analog and memory unit cells | Sumanth Kamineni Arvind Sharma Ramesh Harjani Sachin S Sapatnekar Benton H Calhoun | 2023/4/17 | |
Minimum unit capacitance calculation for binary-weighted capacitor arrays | Nibedita Karmokar Ramesh Harjani Sachin S Sapatnekar | 2023/4/17 | |
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology | Meghna Madhusudan Jitesh Poojary Arvind K Sharma S Ramprasath Kishor Kunal | 2023/9/11 | |
Machine Learning for Analog Layout | Steven M Burns Hao Chen Tonmoy Dhar Ramesh Harjani Jiang Hu | 2022/8/10 | |
Common-centroid layout for active and passive devices: A review and the road ahead | Nibedita Karmokar Meghna Madhusudan Arvind K Sharma Ramesh Harjani Mark Po-Hung Lin | 2022/1/17 | |
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. | S Ramprasath Meghna Madhusudan Arvind K Sharma Jitesh Poojary Soner Yaldiz | 2022/4/13 | |
Constructive common-centroid placement and routing for binary-weighted capacitor arrays | Nibedita Karmokar Arvind K Sharma Jitesh Poojary Meghna Madhusudan Ramesh Harjani | 2022/3/14 | |
A charge flow formulation for guiding analog/mixed-signal placement | Tonmoy Dhar S Ramprasath Jitesh Poojary Soner Yaldiz Steven Burns | 2022/3/14 | |
Performance-driven wire sizing for analog integrated circuits | ACM Transactions on Design Automation of Electronic Systems | Yaguang Li Yishuang Lin Meghna Madhusudan Arvind Sharma Sachin Sapatnekar | 2022/12/24 |
Are analytical techniques worthwhile for analog IC placement? | Yishuang Lin Yaguang Li Donghao Fang Meghna Madhusudan Sachin S Sapatnekar | 2022/3/14 | |
DC-DC Power Converter Designs | Ramesh Harjani | 2022/9/1 | |
Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS | IEEE Transactions on Circuits and Systems II: Express Briefs | Sanggeun Lee Ramesh Harjani Taehyoun Oh | 2022/1/21 |
Co-Authors
