Qiaochu Zhang

Qiaochu Zhang

University of Southern California

H-index: 7

North America-United States

About Qiaochu Zhang

Qiaochu Zhang, With an exceptional h-index of 7 and a recent h-index of 7 (since 2020), a distinguished researcher at University of Southern California, specializes in the field of Mixed-Signal Circuits, Electronic Design Automation.

His recent articles reflect a diverse array of research interests and contributions to the field:

Boolean satisfiability circuit accelerator

Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS

A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems

14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture

Qiaochu Zhang Information

University

Position

___

Citations(all)

154

Citations(since 2020)

140

Cited By

44

hIndex(all)

7

hIndex(since 2020)

7

i10Index(all)

5

i10Index(since 2020)

4

Email

University Profile Page

Google Scholar

Qiaochu Zhang Skills & Research Interests

Mixed-Signal Circuits

Electronic Design Automation

Top articles of Qiaochu Zhang

Boolean satisfiability circuit accelerator

2024/4/4

Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration

IEEE Journal of Solid-State Circuits

2023/10/10

Qiaochu Zhang
Qiaochu Zhang

H-Index: 2

Shiyu Su
Shiyu Su

H-Index: 5

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS

2023/9/11

A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC

2023/4/23

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems

2023/4/23

14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur

2023/2/19

Qiaochu Zhang
Qiaochu Zhang

H-Index: 2

Shiyu Su
Shiyu Su

H-Index: 5

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling

2022/7/10

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture

2021/12/15

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

2021/12/15

Circuit connectivity inspired neural network for analog mixed-signal functional modeling

2021/12/5

From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning

2021/11/1

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration

IEEE Journal of Solid-State Circuits

2021/7/27

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur

2021/2/13

Transfer learning with Bayesian optimization-aided sampling for efficient AMS circuit modeling

2020/11/2

CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation

2020/11

Qiaochu Zhang
Qiaochu Zhang

H-Index: 2

Shiyu Su
Shiyu Su

H-Index: 5

See List of Professors in Qiaochu Zhang University(University of Southern California)

Co-Authors

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