Angelo Parisi
Politecnico di Milano
H-index: 5
Europe-Italy
Top articles of Angelo Parisi
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
IEEE Transactions on Circuits and Systems II: Express Briefs
2022/6/10
Digitally assisted frequency synthesizers and data converters for wide-band radio systems
2022/1/25
Angelo Parisi
H-Index: 2
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters
2022/6/19
A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping
IEEE Journal of Solid-State Circuits
2021/10/11
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits
2021/7/19
Angelo Parisi
H-Index: 2
Luca Bertulessi
H-Index: 6
Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators
IEEE Microwave and Wireless Components Letters
2021/7/2
32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021/2/13
32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter
2021/2/13
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
2021
Angelo Parisi
H-Index: 2
Mario Mercandelli
H-Index: 4
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
IEEE Journal of Solid-State Circuits
2020/9/3
Mario Mercandelli
H-Index: 4
Luca Bertulessi
H-Index: 6
Angelo Parisi
H-Index: 2
Salvatore Levantino
H-Index: 21
17.5 A 12.5 GHz fractional-N type-I sampling PLL achieving 58fs integrated jitter
2020/2/16
Mario Mercandelli
H-Index: 4
Angelo Parisi
H-Index: 2
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
Co-Authors
