Luca Bertulessi
Politecnico di Milano
H-index: 10
Europe-Italy
Top articles of Luca Bertulessi
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Hardware Accelerator for Feature Extraction from sensors’ physical signals | L Bertulessi D Nucera T Maioli | 2023 | |
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity | Lorenzo Scaletti Luca Bertulessi Andrea Cristofoli Andrea Bonfanti | 2023/6/26 | |
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9 dB SFDR in 28nm CMOS | Luca Ricci Lorenzo Scaletti Gabriele Bè Michele Rocco Luca Bertulessi | 2023/6/11 | |
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays | IEEE Journal of Solid-State Circuits | Francesco Tesolin Simone M Dartizio Francesco Buccoleri Alessio Santiccioli Luca Bertulessi | 2023/5/17 |
4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering | Simone M Dartizio Francesco Tesolin Giacomo Castoro Francesco Buccoleri Luca Lanzoni | 2023/2/19 | |
4.5 A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology | Giacomo Castoro Simone M Dartizio Francesco Tesolin Francesco Buccoleri Michele Rossoni | 2023/2/19 | |
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization | IEEE Transactions on Circuits and Systems II: Express Briefs | Gabriele Zanoletti Lorenzo Scaletti Gabriele Bè Luca Ricci Michele Rocco | 2023/11/28 |
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs | Luca Ricci Lorenzo Scaletti Gabriele Bè Luca Bertulessi Salvatore Levantino | 2022/5/27 | |
A digital PLL with multitap LMS-based bandwidth control | IEEE Solid-State Circuits Letters | Mario Mercandelli Luca Bertulessi Carlo Samori Salvatore Levantino | 2022/5/9 |
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner | IEEE Journal of Solid-State Circuits | Francesco Buccoleri Simone M Dartizio Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/12/22 |
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler | Francesco Buccoleri Simone M Dartizio Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/4/24 | |
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … | IEEE Journal of Solid-State Circuits | Simone M Dartizio Francesco Buccoleri Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/10/3 |
A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching | Simone Mattia Dartizio Francesco Buccoleri Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/2/20 | |
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters | Lorenzo Scaletti Gabriele Bè Angelo Parisi Luca Bertulessi Luca Ricci | 2022/6/19 | |
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise | IEEE Transactions on Circuits and Systems I: Regular Papers | Luca Bertulessi Dmytro Cherniak Mario Mercandelli Carlo Samori Andrea L Lacaita | 2022/2/3 |
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations | IEEE Transactions on Circuits and Systems II: Express Briefs | Gabriele Bè Angelo Parisi Luca Bertulessi Luca Ricci Lorenzo Scaletti | 2022/6/10 |
Circuito integrato per l'estrazione di caratteristiche di segnale | L Bertulessi T Maioli D Nucera | 2022 | |
Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications | Special Topics in Information Technology | Luca Bertulessi | 2021 |
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits | Lorenzo Scaletti Angelo Parisi Luca Bertulessi | 2021/7/19 | |
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter | IEEE Journal of Solid-State Circuits | Mario Mercandelli Alessio Santiccioli Angelo Parisi Luca Bertulessi Dmytro Cherniak | 2021/11/13 |
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