Bevilacqua Andrea
Università degli Studi di Padova
H-index: 28
Europe-Italy
Top articles of Bevilacqua Andrea
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband | IEEE Transactions on Circuits and Systems II: Express Briefs | Luca Bellemo Andrea Bevilacqua | 2024/3/13 |
A Time-Variant Analysis of Passive Resistive Mixers Using Thévenin Theorem | Lorenzo Tomasin Andrea Bevilacqua | 2023/6/18 | |
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies | NicolÒ Zugno Francesco Brandonisio Thomas Niederfriniger Andrea Bevilacqua | 2023/6/18 | |
A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS | Lorenzo Tomasin Daniele Vogrig Andrea Neviani Andrea Bevilacqua | 2023/6/11 | |
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs | IEEE Journal of Solid-State Circuits | Agata Iesurum Davide Manente Fabio Padovan Matteo Bassi Andrea Bevilacqua | 2023/6/6 |
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters | IEEE Transactions on Microwave Theory and Techniques | Lorenzo Tomasin Daniele Vogrig Andrea Neviani Andrea Bevilacqua | 2023/12/18 |
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures | IEEE Transactions on Circuits and Systems I: Regular Papers | Davide Manente Fabio Quadrelli Fabio Padovan Matteo Bassi Andrea Mazzanti | 2022/11/15 |
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler | Francesco Buccoleri Simone M Dartizio Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/4/24 | |
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … | IEEE Journal of Solid-State Circuits | Simone M Dartizio Francesco Buccoleri Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/10/3 |
A Broadband 22–31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications | IEEE Journal of Solid-State Circuits | Fabio Quadrelli Davide Manente David Seebacher Fabio Padovan Matteo Bassi | 2022/4/1 |
A 24 GHz Quadrature VCO Based on Coupled PLL with-134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS | Agata Iesurum Davide Manente Fabio Padovan Matteo Bassi Andrea Bevilacqua | 2022/9/19 | |
A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching | Simone Mattia Dartizio Francesco Buccoleri Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/2/20 | |
Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing | IEEE Transactions on Microwave Theory and Techniques | Chengyao Shi Minyoung Song Zhenyu Gao Andrea Bevilacqua Guido Dolmans | 2022/8/22 |
Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices | IEEE Transactions on Electron Devices | N Modolo C De Santi Giulio Baratella A Bettini M Borga | 2022/6/30 |
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner | IEEE Journal of Solid-State Circuits | Francesco Buccoleri Simone M Dartizio Francesco Tesolin Luca Avallone Alessio Santiccioli | 2022/12/22 |
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise | IEEE Journal of Solid-State Circuits | Lorenzo Tomasin Pietro Andreani Giovanni Boi Fabio Padovan Andrea Bevilacqua | 2022/4/26 |
A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS | IEEE Microwave and Wireless Components Letters | Alessandro Franceschin Fabio Quadrelli Fabio Padovan Matteo Bassi Andrea Mazzanti | 2021/8/11 |
A Multichannel D-Band Radar Receiver With Optimized LO Distribution | IEEE Solid-State Circuits Letters | Andrea Bilato Vadim Issakov Andrea Mazzanti Andrea Bevilacqua | 2021/7/21 |
A 10.7–14.1 GHz Reconfigurable Octacore DCO with− 126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS | Lorenzo Tomasin Giovanni Boi Fabio Padovan Andrea Bevilacqua | 2021/6/7 | |
Session 20 Overview: High-Performance VCOs | Andrea Bevilacqua Salvatore Levantino Hua Wang | 2021/2/13 |
Co-Authors
