Mario Mercandelli
Politecnico di Milano
H-index: 8
Europe-Italy
Top articles of Mario Mercandelli
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters | Lorenzo Scaletti Gabriele Bè Angelo Parisi Luca Bertulessi Luca Ricci | 2022/6/19 | |
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations | IEEE Transactions on Circuits and Systems II: Express Briefs | Gabriele Bè Angelo Parisi Luca Bertulessi Luca Ricci Lorenzo Scaletti | 2022/6/10 |
A digital PLL with multitap LMS-based bandwidth control | IEEE Solid-State Circuits Letters | Mario Mercandelli Luca Bertulessi Carlo Samori Salvatore Levantino | 2022/5/9 |
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise | IEEE Transactions on Circuits and Systems I: Regular Papers | Luca Bertulessi Dmytro Cherniak Mario Mercandelli Carlo Samori Andrea L Lacaita | 2022/2/3 |
Radar signal modulator with bandwidth compensation and frequency offset sequence | 2022/9/27 | ||
A 3.7-to-4.1 GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter | Mario Mercandelli Luca Bertulessi Carlo Samori Salvatore Levantino | 2021/11/7 | |
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs | IEEE Transactions on Circuits and Systems I: Regular Papers | Luca Avallone Mario Mercandelli Alessio Santiccioli Michael Peter Kennedy Salvatore Levantino | 2021/4/16 |
32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays | Alessio Santiccioli Mario Mercandelli Simone M Dartizio Francesco Tesolin Saleh Karman | 2021/2/13 | |
A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping | IEEE Journal of Solid-State Circuits | Simone M Dartizio Francesco Tesolin Mario Mercandelli Alessio Santiccioli Abanob Shehata | 2021/10/11 |
32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter | Mario Mercandelli Alessio Santiccioli Simone Mattia Dartizio Abanob Shehata Francesco Tesolin | 2021/2/13 | |
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter | Gabriele Be Mario Mercandelli Luca Bertulessi | 2021/7/19 | |
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity | Angelo Parisi Mario Mercandelli Carlo Samori Andrea L Lacaita | 2021 | |
Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators | IEEE Microwave and Wireless Components Letters | A Parisi F Tesolin M Mercandelli L Bertulessi AL Lacaita | 2021/7/2 |
A 18.9-22.3 GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability | Saleh Karman Francesco Tesolin Alessandro Dago Mario Mercandelli Carlo Samori | 2021/6/7 | |
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter | IEEE Journal of Solid-State Circuits | Mario Mercandelli Alessio Santiccioli Angelo Parisi Luca Bertulessi Dmytro Cherniak | 2021/11/13 |
A 250-Mb/s Direct Phase Modulator With− 42.4-dB EVM Based on a 14-GHz Digital PLL | IEEE Solid-State Circuits Letters | Dmytro Cherniak Mario Mercandelli Luca Bertulessi Fabio Padovan Luigi Grimaldi | 2020/7/2 |
Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis | MARIO MERCANDELLI | 2020/2/3 | |
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking | IEEE Journal of Solid-State Circuits | Alessio Santiccioli Mario Mercandelli Luca Bertulessi Angelo Parisi Dmytro Cherniak | 2020/9/3 |
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