Luca Bertulessi
Politecnico di Milano
H-index: 10
Europe-Italy
Top articles of Luca Bertulessi
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization
IEEE Transactions on Circuits and Systems II: Express Briefs
2023/11/28
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity
2023/6/26
Luca Bertulessi
H-Index: 6
Andrea Bonfanti
H-Index: 13
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9 dB SFDR in 28nm CMOS
2023/6/11
Luca Ricci
H-Index: 5
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
Andrea Bonfanti
H-Index: 13
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
IEEE Journal of Solid-State Circuits
2023/5/17
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023/2/19
4.5 A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
2023/2/19
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
Hardware Accelerator for Feature Extraction from sensors’ physical signals
2023
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
IEEE Journal of Solid-State Circuits
2022/12/22
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking …
IEEE Journal of Solid-State Circuits
2022/10/3
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters
2022/6/19
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
IEEE Transactions on Circuits and Systems II: Express Briefs
2022/6/10
Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs
2022/5/27
Luca Ricci
H-Index: 5
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
Andrea Bonfanti
H-Index: 13
A digital PLL with multitap LMS-based bandwidth control
IEEE Solid-State Circuits Letters
2022/5/9
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
2022/4/24
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching
2022/2/20
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
IEEE Transactions on Circuits and Systems I: Regular Papers
2022/2/3
Circuito integrato per l'estrazione di caratteristiche di segnale
2022
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
IEEE Journal of Solid-State Circuits
2021/11/13
Mario Mercandelli
H-Index: 4
Angelo Parisi
H-Index: 2
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
A 3.7-to-4.1 GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
2021/11/7
A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping
IEEE Journal of Solid-State Circuits
2021/10/11
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