Mario Mercandelli
Politecnico di Milano
H-index: 8
Europe-Italy
Top articles of Mario Mercandelli
Radar signal modulator with bandwidth compensation and frequency offset sequence
2022/9/27
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters
2022/6/19
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
IEEE Transactions on Circuits and Systems II: Express Briefs
2022/6/10
A digital PLL with multitap LMS-based bandwidth control
IEEE Solid-State Circuits Letters
2022/5/9
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
IEEE Transactions on Circuits and Systems I: Regular Papers
2022/2/3
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
IEEE Journal of Solid-State Circuits
2021/11/13
Mario Mercandelli
H-Index: 4
Angelo Parisi
H-Index: 2
Luca Bertulessi
H-Index: 6
Salvatore Levantino
H-Index: 21
A 3.7-to-4.1 GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
2021/11/7
A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping
IEEE Journal of Solid-State Circuits
2021/10/11
Mario Mercandelli
H-Index: 4
Saleh Karman
H-Index: 3
Luca Bertulessi
H-Index: 6
Angelo Parisi
H-Index: 2
Salvatore Levantino
H-Index: 21
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter
2021/7/19
Mario Mercandelli
H-Index: 4
Luca Bertulessi
H-Index: 6
Self-Biasing Dynamic Startup Circuit for Current-Biased Class-C Oscillators
IEEE Microwave and Wireless Components Letters
2021/7/2
A 18.9-22.3 GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability
2021/6/7
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs
IEEE Transactions on Circuits and Systems I: Regular Papers
2021/4/16
32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021/2/13
32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter
2021/2/13
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
2021
Angelo Parisi
H-Index: 2
Mario Mercandelli
H-Index: 4
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
IEEE Journal of Solid-State Circuits
2020/9/3
Mario Mercandelli
H-Index: 4
Luca Bertulessi
H-Index: 6
Angelo Parisi
H-Index: 2
Salvatore Levantino
H-Index: 21
A 250-Mb/s Direct Phase Modulator With− 42.4-dB EVM Based on a 14-GHz Digital PLL
IEEE Solid-State Circuits Letters
2020/7/2
Techniques for low-jitter and low-area occupation fractional-N Frequency synthesis
2020/2/3
Mario Mercandelli
H-Index: 4
Co-Authors
