Hongwu Jiang
Georgia Institute of Technology
H-index: 15
North America-United States
Top articles of Hongwu Jiang
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators
ACM Transactions on Design Automation of Electronic Systems
2023/5/1
Hongwu Jiang
H-Index: 4
Shimeng Yu
H-Index: 54
Architecture and Circuit Design Optimization for Compute-In-Memory
2022/11/21
Hongwu Jiang
H-Index: 4
MAC-ECC: In-situ error correction and its design methodology for reliable NVM-based compute-in-memory inference engine
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
2022/11/17
ENNA: An efficient neural network accelerator design based on ADC-free compute-in-memory subarrays
IEEE Transactions on Circuits and Systems I: Regular Papers
2022/10/10
A 40nm RRAM compute-in-memory macro with parallelism-preserving ECC for iso-accuracy voltage scaling
2022/9/19
A 40nm analog-input ADC-free compute-in-memory RRAM macro with pulse-width modulation between sub-arrays
2022/6/12
A 40-nm MLC-RRAM compute-in-memory macro with sparsity control, on-chip write-verify, and temperature-independent ADC references
IEEE Journal of Solid-State Circuits
2022/4/12
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
2022/3/8
Secure XOR-CIM engine: Compute-in-memory sram architecture with embedded xor encryption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2021/10/26
A 40nm RRAM compute-in-memory macro featuring on-chip write-verify and offset-cancelling ADC references
2021/9/13
Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips
IEEE Journal of Solid-State Circuits
2021/9/10
Mitigating adversarial attack for compute-in-memory accelerator utilizing on-chip finetune
2021/8/18
Hongwu Jiang
H-Index: 4
Shimeng Yu
H-Index: 54
Compute-in-memory chips for deep learning: Recent trends and prospects
2021/8/13
NeuroSim simulator for compute-in-memory hardware accelerator: Validation and benchmark
Frontiers in artificial intelligence
2021/6/9
NeuroSim validation with 40nm RRAM compute-in-memory macro
2021/6/6
Exploiting process variations to protect machine learning inference engine from chip cloning
2021/5/22
Secure-RRAM: A 40nm 16kb compute-in-memory macro with reconfigurability, sparsity control, and embedded security
2021/4/25
Analog-to-digital converter design exploration for compute-in-memory accelerators
IEEE Design & Test
2021/1/11
DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2020/12/14
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