Yibo Lin
Peking University
H-index: 29
Asia-China
Top articles of Yibo Lin
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning
2024
Heterogeneous Static Timing Analysis with Advanced Delay Calculator
cell
2024
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction
arXiv preprint arXiv:2403.18569
2024/3/27
Analytical Heterogeneous Die-to-Die 3D Placement with Macros
arXiv preprint arXiv:2403.09070
2024/3/14
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells
2024/3/12
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models
arXiv preprint arXiv:2403.07257
2024/3/12
Lei Chen
H-Index: 18
Tsung-Yi Ho
H-Index: 30
Yu Huang
H-Index: 2
Min Li
H-Index: 16
Yun Liang
H-Index: 2
Yibo Lin
H-Index: 15
Yi Liu
H-Index: 21
Guojie Luo
H-Index: 15
Guangyu Sun
H-Index: 9
Runsheng Wang
H-Index: 7
Ziyi Wang
H-Index: 3
Zhiyao Xie
H-Index: 3
Qiang Xu
H-Index: 10
Bei Yu
H-Index: 14
Zuodong Zhang
H-Index: 2
Hui-Ling Zhen
H-Index: 15
Ziyang Zheng
H-Index: 2
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs
2024/3/12
IncreMacro: Incremental Macro Placement Refinement
2024/3/12
An Efficient Task-Parallel Pipeline Programming Framework
2024/1/18
Zizheng Guo
H-Index: 1
Yibo Lin
H-Index: 15
Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2023/12/26
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
IEEE Transactions on Circuits and Systems I: Regular Papers
2023/12/18
Lin Chen
H-Index: 21
Yibo Lin
H-Index: 15
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2023/12/13
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction
IEEE Transactions on Circuits and Systems II: Express Briefs
2023/11/28
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation
2023/10/28
Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms
2023/10/28
Stronger Mixed-Size Placement Backbone Considering Second-Order Information
2023/10/28
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction
2023/10/28
OpenPARF: an open-source placement and routing framework for large-scale heterogeneous FPGAs with deep learning toolkit
2023/10/24
Post-Layout Simulation Driven Analog Circuit Sizing
arXiv preprint arXiv:2310.14049
2023/10/21
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment
2023/10/13
Co-Authors
