SAPTADEEP PAL

SAPTADEEP PAL

University of California, Los Angeles

H-index: 11

North America-United States

About SAPTADEEP PAL

SAPTADEEP PAL, With an exceptional h-index of 11 and a recent h-index of 10 (since 2020), a distinguished researcher at University of California, Los Angeles, specializes in the field of High Performance System/Computer Architecture, VLSI Design, Physical Design.

His recent articles reflect a diverse array of research interests and contributions to the field:

DeepFlow: A cross-stack pathfinding framework for distributed ai systems

Chiplets: How Small is too Small?

TSV-less Power Delivery for Wafer-scale Assemblies and Interposers

Scale-Out Packageless Processing

Designing a 2048-chiplet, 14336-core waferscale processor

I/o architecture, substrate design, and bonding process for a heterogeneous dielet-assembly based waferscale processor

Flexible connectors and PCB segmentation for signaling and power delivery in wafer-scale systems

Copper to gold thermal compression bonding in heterogenous wafer-scale systems

SAPTADEEP PAL Information

University

Position

Electrical and Computer Engineering

Citations(all)

458

Citations(since 2020)

386

Cited By

205

hIndex(all)

11

hIndex(since 2020)

10

i10Index(all)

12

i10Index(since 2020)

11

Email

University Profile Page

University of California, Los Angeles

Google Scholar

View Google Scholar Profile

SAPTADEEP PAL Skills & Research Interests

High Performance System/Computer Architecture

VLSI Design

Physical Design

Top articles of SAPTADEEP PAL

Title

Journal

Author(s)

Publication Date

DeepFlow: A cross-stack pathfinding framework for distributed ai systems

ACM Transactions on Design Automation of Electronic Systems

Newsha Ardalani

Saptadeep Pal

Puneet Gupta

2024/2/15

Chiplets: How Small is too Small?

Alexander Graening

Saptadeep Pal

Puneet Gupta

2023/7/9

TSV-less Power Delivery for Wafer-scale Assemblies and Interposers

Haoxiang Ren

Saptadeep Pal

Guangqi Ouyang

Randall Irwin

Yu-Tao Yang

...

2022/5/31

Scale-Out Packageless Processing

Saptadeep Pal

2021

Designing a 2048-chiplet, 14336-core waferscale processor

Saptadeep Pal

Jingyang Liu

Irina Alam

Nicholas Cebry

Haris Suhail

...

2021/12/5

I/o architecture, substrate design, and bonding process for a heterogeneous dielet-assembly based waferscale processor

Saptadeep Pal

Irina Alam

Krutikesh Sahoo

Haris Suhail

Rakesh Kumar

...

2021/6/1

Flexible connectors and PCB segmentation for signaling and power delivery in wafer-scale systems

Randall Irwin

Krutikesh Sahoo

Saptadeep Pal

Subramanian S Iyer

2021/6/1

Copper to gold thermal compression bonding in heterogenous wafer-scale systems

Krutikesh Sahoo

Saptadeep Pal

Niloofar Shakoorzadeh

Yu-Tao Yang

Subramanian S Iyer

2021/6/1

Parallelization strategies for training a neural network

2020/11/26

Pathfinding for 2.5 D interconnect technologies

Saptadeep Pal

Puneet Gupta

2020/11/5

Design space exploration for chiplet-assembly-based processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Saptadeep Pal

Daniel Petrisko

Rakesh Kumar

Puneet Gupta

2020/2/13

See List of Professors in SAPTADEEP PAL University(University of California, Los Angeles)

Co-Authors

H-index: 62
SUBRAMANIAN S. IYER

SUBRAMANIAN S. IYER

University of California, Los Angeles

H-index: 29
Sudhakar Pamarti

Sudhakar Pamarti

University of California, Los Angeles

H-index: 12
SivaChandra Jangam

SivaChandra Jangam

University of California, Los Angeles

H-index: 6
Daniel Petrisko

Daniel Petrisko

University of Washington

H-index: 5
Irina Alam

Irina Alam

University of California, Los Angeles

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