Hyunyoon Cho
Seoul National University
H-index: 6
Asia-South Korea
Top articles of Hyunyoon Cho
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Transmitter circuit and method of operating same | 2024/2/27 | ||
Translation device, test system including the same, and memory system including the translation device | 2024/1/9 | ||
Memory device, memory system, and operation method of memory device | 2023/3/2 | ||
Clock converting circuit with symmetric structure | 2023/9/7 | ||
Semiconductor devices having parallel-to-serial converters therein | 2023/12/14 | ||
Memory device for generating pulse amplitude modulation-based DQ signal and memory system including the same | 2023/2/21 | ||
Memory device, controller controlling the same, memory system including the same, and operating method thereof | 2023/5/23 | ||
Method of generating a multi-level signal using selective equalization, method of transmitting data using the same, and transmitter and memory system performing the same | 2023/12/7 | ||
Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers | 2023/2/7 | ||
Memory device and method for calibrating the device and fabricating the device | 2023/5/11 | ||
Semiconductor memory device and memory | 2023/11/9 | ||
Receiver for receiving multi-level signal and memory device including the same | 2023/4/20 | ||
Transmitter circuit including selection circuit, and method of operating the selection circuit | 2023/10/31 | ||
Receiver with pipeline structure for receiving multi-level signal and memory device including the same | 2023/4/13 | ||
Delay circuit and clock error correction device including the same | 2023/10/17 | ||
Memory device and memory system | 2022/10/4 | ||
A 40-Gb/s/pin low-voltage POD single-ended PAM-4 transceiver with timing calibrated reset-less slicer and bidirectional T-coil for GDDR7 application | Hyunsub Norbert Rie Chang Soo Yoon Jindo Byun Sucheol Lee Garam Kim | 2022/6/12 | |
A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process | Joohwan Kim Junyoung Park Jindo Byun Changkyu Seol Chang Soo Yoon | 2022/4/24 | |
A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE | Hyungmin Jin Jindo Byun Hyunyoon Cho Hojun Yoon Jin-Hee Park | 2021/11/7 | |
Output drivers and semiconductor memory devices having the same | 2021/10/19 |
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