Vojtech Mrazek

Vojtech Mrazek

Vysoké ucení technické v Brne

H-index: 20

Europe-Czech Republic

About Vojtech Mrazek

Vojtech Mrazek, With an exceptional h-index of 20 and a recent h-index of 19 (since 2020), a distinguished researcher at Vysoké ucení technické v Brne, specializes in the field of evolutionary design, hardware, embedded systems, VLSI.

His recent articles reflect a diverse array of research interests and contributions to the field:

ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators

2024 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Adee-lid: Automated design of energy-efficient hardware accelerators for levodopa-induced dyskinesia classifiers

Hardware and Software Optimizations for Capsule Networks

autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification

Acceleration techniques for automated design of approximate convolutional neural networks

Vojtech Mrazek Information

University

Position

Post-doc researcher

Citations(all)

1482

Citations(since 2020)

1290

Cited By

581

hIndex(all)

20

hIndex(since 2020)

19

i10Index(all)

31

i10Index(since 2020)

27

Email

University Profile Page

Vysoké ucení technické v Brne

Google Scholar

View Google Scholar Profile

Vojtech Mrazek Skills & Research Interests

evolutionary design

hardware

embedded systems

VLSI

Top articles of Vojtech Mrazek

Title

Journal

Author(s)

Publication Date

ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers

arXiv preprint arXiv:2404.08002

Michal Pinos

Lukas Sekanina

Vojtech Mrazek

2024/4/8

Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators

Jan Klhufek

Miroslav Safar

Vojtech Mrazek

Zdenek Vasicek

Lukas Sekanina

2024/4/3

2024 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Stanisław Deniziak

Paweł Sitek

Maksim Jenihhin

Andreas Steininger

Mario Schölzel

...

2024

Adee-lid: Automated design of energy-efficient hardware accelerators for levodopa-induced dyskinesia classifiers

Martin Hurta

Vojtech Mrazek

Michaela Drahosova

Lukas Sekanina

2023/4/17

Hardware and Software Optimizations for Capsule Networks

Alberto Marchisio

Beatrice Bussolino

Alessio Colucci

Vojtech Mrazek

Muhammad Abdullah Hanif

...

2023/10/10

autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

arXiv preprint arXiv:2303.04734

Bharath Srinivas Prabakaran

Vojtech Mrazek

Zdenek Vasicek

Lukas Sekanina

Muhammad Shafique

2023/3/8

Effective EEG Feature Selection for Interpretable MDD (Major Depressive Disorder) Classification

Vojtech Mrazek

Soyiba Jawed

Muhammad Arif

Aamir Saeed Malik

2023/7/15

Acceleration techniques for automated design of approximate convolutional neural networks

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Michal Pinos

Vojtech Mrazek

Filip Vaverka

Zdenek Vasicek

Lukas Sekanina

2023/1/9

Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits

Michal Pinos

Vojtech Mrazek

Lukas Sekanina

2023/5/3

MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers

Martin Hurta

Vojtech Mrazek

Michaela Drahosova

Lukas Sekanina

2023/5/3

Hardware-Aware Evolutionary Approaches to Deep Neural Networks

Lukas Sekanina

Vojtech Mrazek

Michal Pinos

2023/11/2

Approximation of Hardware Accelerators driven by Machine-Learning Models:(Embedded Tutorial)

Vojtech Mrazek

2023/5/3

Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

Bharath Srinivas Prabakaran

Vojtech Mrazek

Zdenek Vasicek

Lukas Sekanina

Muhammad Shafique

2023/10/28

Inexact Arithmetic Operators

Lukas Sekanina

Zdenek Vasicek

Vojtech Mrazek

2022/1/3

Designing Approximate Arithmetic Circuits with Combined Error Constraints

Milan Češka

Jiří Matyáš

Vojtech Mrazek

Tomáš Vojnar

2022/8/31

Evolutionary design of reduced precision preprocessor for levodopa-induced dyskinesia classifier

Martin Hurta

Michaela Drahosova

Vojtech Mrazek

2022/8/14

Optimization of BDD-based approximation error metrics calculations

Vojtech Mrazek

2022/7/4

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

Jan Klhufek

Vojtech Mrazek

2022/4/6

Rohnas: A neural architecture search framework with conjoint optimization for adversarial robustness and hardware efficiency of convolutional and capsule networks

IEEE Access

Alberto Marchisio

Vojtech Mrazek

Andrea Massa

Beatrice Bussolino

Maurizio Martina

...

2022/10/13

Approximate Computing Architectures

Muhammad Abdullah Hanif

Vojtech Mrazek

Muhammad Shafique

2022/1/27

See List of Professors in Vojtech Mrazek University(Vysoké ucení technické v Brne)

Co-Authors

H-index: 52
Muhammad Shafique

Muhammad Shafique

New York University

H-index: 38
Lukas Sekanina

Lukas Sekanina

Vysoké ucení technické v Brne

H-index: 31
Tomas Vojnar

Tomas Vojnar

Vysoké ucení technické v Brne

H-index: 28
Zdenek Vasicek

Zdenek Vasicek

Vysoké ucení technické v Brne

H-index: 21
Milan Ceska

Milan Ceska

Vysoké ucení technické v Brne

H-index: 17
Alberto Marchisio

Alberto Marchisio

Technische Universität Wien

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