Seung-Tak Ryu
KAIST
H-index: 31
Asia-South Korea
Top articles of Seung-Tak Ryu
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling | IEEE Journal of Solid-State Circuits | Dong-Hun Lee Kent Edrian Lozada Ye-Dam Kim Ho-Jin Kim Youngjae Cho | 2024/4/30 |
Continuous time operation amplifier and operating method | 2024/4/11 | ||
Amplification apparatus, integration apparatus and modulation apparatus each including duty-cycled resistor | 2024/2/27 | ||
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC | IEEE Journal of Solid-State Circuits | Jae-Hyun Chung Ye-Dam Kim Chang-Un Park Kun-Woo Park Dong-Ryeol Oh | 2024/2/8 |
An 81.2 dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC | Jae-Hyun Chung Ye-Dam Kim Chang-Un Park Kun-Woo Park Min-Jae Seo | 2023/4/23 | |
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1–0 MASH and DNC | Kent Edrian Lozada Dong-Hun Lee Ye-Dam Kim Ho-Jin Kim Youngjae Cho | 2023/11/5 | |
Large scale terahertz sensor array module with antenna coupled microbolometers on glass substrate with sigma delta ADC readout ASIC | IEEE Transactions on Terahertz Science and Technology | John Hong Sean Andrews Jan Bos Edward Chan Tallis Chang | 2023/4/5 |
Analog-to-digital converter, method of analog-to-digital conversion, and electronic apparatus | 2023/9/14 | ||
Readout circuits and methods | 2023/7/27 | ||
Design of a Continuous-Time Delta-Sigma Modulator for Bio-signal Acquisition | Journal of Integrated Circuits and Systems | Ye-Dam Kim Seung-Tak Ryu | 2023/6/30 |
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration | Chang-Un Park Jae-Hyun Chung Seung-Tak Ryu | 2023/4/23 | |
A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling | IEEE Journal of Solid-State Circuits | Taewook Kim Changsok Han Nima Maghari | 2017/8/29 |
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs | Dong-Jin Chang Seung-Tak Ryu | 2022/6/12 | |
A 7-bit two-step flash ADC with sample-and-hold sharing technique | IEEE Journal of Solid-State Circuits | Dong-Ryeol Oh Min-Jae Seo Seung-Tak Ryu | 2022/4/1 |
Analog-to-digital converter | 2021/2/23 | ||
A 4th-order CT I-DSM with digital noise coupling and input pre-conversion method for initialization | Ye-Dam Kim Jae-Hyun Chung Kent Edrian Lozada Dong-Jin Chang Seung-Tak Ryu | 2021/11/7 | |
Brief overview on design techniques and architectures of SAR ADCs | Kunwoo Park Dong-Jin Chang Seung-Tak Ryu | 2021 | |
An input-buffer embedding dual-residue pipelined-SAR ADC with nonbinary capacitive interpolation | Seung-Yong Lim Raymond Mabilangan Dong-Jin Chang Young-Jae Cho Michael Choi | 2021/11/7 | |
Analog-digital converter and semiconductor memory device having the same | 2021/9/28 | ||
MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs | IEEE Access | Dong-Jin Chang Byeong-Gyu Nam Seung-Tak Ryu | 2021/8/23 |
Co-Authors
