Nachiket Kapre

University of Waterloo

H-index: 26

North America-Canada

About Nachiket Kapre

Nachiket Kapre, With an exceptional h-index of 26 and a recent h-index of 17 (since 2020), a distinguished researcher at University of Waterloo, specializes in the field of Reconfigurable Computing, FPGAs, Spatial Processing, Parallel Processing.

His recent articles reflect a diverse array of research interests and contributions to the field:

Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems

HopliteML: Evolving application customized FPGA NoCs with adaptable routers and regulators

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs

Digital circuits for evaluating neural engineering framework style neural networks

Rapid Layout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Worst-case latency analysis for the versal NoC network packet switch

Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs

Nachiket Kapre Information

University	University of Waterloo
Position	___
Citations(all)	2346
Citations(since 2020)	1045
Cited By	1779
hIndex(all)	26
hIndex(since 2020)	17
i10Index(all)	53
i10Index(since 2020)	34
Email	Access Email
University Profile Page	University of Waterloo
Google Scholar	View Google Scholar Profile

Nachiket Kapre Skills & Research Interests

Reconfigurable Computing

FPGAs

Spatial Processing

Parallel Processing

Top articles of Nachiket Kapre

Title	Journal	Author(s)	Publication Date
Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems		Zhuanhao Wu Marat Bekmyrza Nachiket Kapre Hiren Patel	2023/4/17
HopliteML: Evolving application customized FPGA NoCs with adaptable routers and regulators	ACM Transactions on Reconfigurable Technology and Systems (TRETS)	Gurshaant Malik Ian Elmore Lang Rodolfo Pellizzoni Nachiket Kapre	2022/8/8
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm	ACM Transactions on Reconfigurable Technology and Systems (TRETS)	Niansong Zhang Xiang Chen Nachiket Kapre	2022/6/6
Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs		Srinirdheeshwar Kuttuva Prakash Hiren Patel Nachiket Kapre	2022/5/15
Digital circuits for evaluating neural engineering framework style neural networks			2022/12/27
Rapid Layout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm	ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS	Nachiket Kapre Niansong Zhang Xiang Chen	2022/12/1
Worst-case latency analysis for the versal NoC network packet switch		Ian Lang Nachiket Kapre Rodolfo Pellizzoni	2021/10/14
Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs		Frederick Tombs Alireza Mellat Nachiket Kapre	2021/5/9
Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers		Gurshaant Malik Ian Elmor Lang Rodolfo Pellizoni Nachiket Kapre	2020/8/1
DarwiNN: efficient distributed neuroevolution under communication constraints		Gurshaant Singh Malik Lucian Petrica Nachiket Kapre Michaela Blott	2020/7/8
Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga Nocs		Ian Lang Ziqiang Huang Nachiket Kapre	2020
HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs	ACM Transactions on Reconfigurable Technology and Systems (TRETS)	Tushar Garg Saud Wasly Rodolfo Pellizzoni Nachiket Kapre	2020/2/13
HopliteRT Source Queuing Bound Correction		Ian Elmor Lang Rodolfo Pellizzoni Nachiket Kapre	2020