Yuncheng Zhang
Tokyo Institute of Technology
H-index: 10
Asia-Japan
Top articles of Yuncheng Zhang
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range | IEEE Solid-State Circuits Letters | Hóngyè Huáng Bangan Liu Zezheng Liu Dingxin Xu Yuncheng Zhang | 2024/1/11 |
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter | IEEE Journal of Solid-State Circuits | Yuncheng Zhang Zheng Sun Bangan Liu Junjun Qiu Dingxin Xu | 2024/1/10 |
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving-62.1 dBc Fractional Spur and 143.7 fs Integrated Jitter | Dingxin Xu Zezheng Liu Yifeng Kuai Hongye Huang Yuncheng Zhang | 2024/2/18 | |
A 2.95 mW/element Ka-band CMOS phased-array receiver utilizing on-chip distributed radiation sensors in low-earth-orbit small satellite constellation | Xi Fu Dongwon You Xiaolin Wang Michihiro Ide Yuncheng Zhang | 2023/2/19 | |
19.4 A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8 dBm EIRP Under 26.6 W Power Consumption Using Single/Dual Circular Polarization … | Dongwon You Xi Fu Xiaolin Wang Yuan Gao Wenqian Wang | 2023/2/19 | |
A 32kHz-reference 2.4 GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration | Junjun Qiu Wenqian Wang Zheng Sun Bangan Liu Yuncheng Zhang | 2023/2/19 | |
A Low-Power 256-Element -Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations | IEEE Journal of Solid-State Circuits | Xi Fu Dongwon You Xiaolin Wang Yun Wang Carolyn Jill Mayeda | 2023/10/2 |
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path | Waleed Madany Yuncheng Zhang Ashbir Aviat Fadila Hongye Huang Junjun Qiu | 2023/9/11 | |
A 6.5-to-8GHz cascaded dual-fractional-N digital PLL achieving-63.7 dBc fractional spurs with 50MHz reference | Dingxin Xu Yuncheng Zhang Hongye Huang Zheng Sun Bangan Liu | 2023/4/23 | |
A CMOS 24–30-GHz low-phase-variation variable gain amplifier design for 5G new radio | IEEE Solid-State Circuits Letters | Junjun Qiu Jian Pang Bangan Liu Xueting Luo Yun Wang | 2022/5/20 |
A 1-bit-DSM-based digital polar power amplifier supporting 1024-QAM | IEEE Solid-State Circuits Letters | Yuncheng Zhang Bangan Liu Junjun Qiu Atsushi Shirane Kenichi Okada | 2022/5/9 |
A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components | IEICE Transactions on Electronics | Yuncheng Zhang Bangan Liu Teruki Someya Rui Wu Junjun Qiu | 2022/7/1 |
A low-power digital baseband circuit for GMSK demodulation in sub-GHz application | IEICE Electronics Express | Junjun Qiu Bangan Liu Yuncheng Zhang Atsushi Shirane Kenichi Okada | 2022/6/25 |
A DSM-based Polar Transmitter with 23.8% System Efficiency | Yuncheng Zhang Bangan Liu Xiaofan Gu Chun Wang Atsushi Shirane | 2021/1/18 | |
A CMOS dual-polarized phased-array beamformer utilizing cross-polarization leakage cancellation for 5G MIMO systems | IEEE Journal of Solid-State Circuits | Jian Pang Zheng Li Xueting Luo Joshua Alvin Rattanan Saengchan | 2021/1/6 |
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth | IEEE Journal of Solid-State Circuits | Junjun Qiu Zheng Sun Bangan Liu Wenqian Wang Dingxin Xu | 2021/9/14 |
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration | Zheng Sun Dingxin Xu Junjun Qiu Zezheng Liu Yuncheng Zhang | 2021/9/13 | |
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal | IEEE Journal of Solid-State Circuits | Yun Wang Dongwon You Xi Fu Takeshi Nakamura Ashbir Aviat Fadila | 2021/7/26 |
A 29% PAE 1.5 Bit-DSM-based polar transmitter with spur-mitigated injection-locked PLL | Yuncheng Zhang Bangan Liu Xiaofan Gu Chun Wang Kiyoshi Yanagisawa | 2020/6/16 | |
A fully-synthesizable fractional-N injection-locked PLL for digital clocking with triangle/sawtooth spread-spectrum modulation capability in 5-nm CMOS | IEEE Solid-State Circuits Letters | Bangan Liu Yuncheng Zhang Junjun Qiu Hongye Huang Zheng Sun | 2020/1/28 |
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