Yang Xiang
University of Guelph
H-index: 26
North America-Canada
Top articles of Yang Xiang
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
CFET SRAM DTCO, interconnect guideline, and benchmark for CMOS scaling | IEEE Transactions on Electron Devices | Hsiao-Hsuan Liu Shairfe M Salahuddin Boon Teik Chan Pieter Schuddinck Yang Xiang | 2023/1/19 |
Stt-mram stochastic and defects-aware dtco for last level cache at advanced process nodes | F García-Redondo S Rao M Gupta M Perumkunnil Y Xiang | 2023/9/11 | |
CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark | IEEE Transactions on Electron Devices | Hsiao-Hsuan Liu Pieter Schuddinck Zhenlin Pei Lynn Verschueren Hans Mertens | 2023/8/24 |
PPA and scaling potential of backside power options in N2 and A14 nanosheet technology | S Yang P Schuddinck M Garcia-Bardon Y Xiang A Veloso | 2023/6/11 | |
Variability in Planar FeFETs—Channel Percolation Impact | IEEE Transactions on Electron Devices | K Kaczmarek M Garcia Bardon Y Xiang N Ronchi L-Å Ragnarsson | 2023/5/29 |
DTCO of sequential and monolithic CFET SRAM | Hsiao-Hsuan Liu Shairfe M Salahuddin Boon Teik Chan Pieter Schuddinck Yang Xiang | 2023/4/28 | |
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch | Pieter Schuddinck Fabian M Bufler Yang Xiang Anita Farokhnejad Gioele Mirabelli | 2022/6/12 | |
Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations | Alessio Spessot Shairfe Muhammad Salahuddin Ricardo Escobar Romain Ritzenthaler Yang Xiang | 2022/5/15 | |
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era | IEEE transactions on very large scale integration (VLSI) systems | Giuliano Sisto Odysseas Zografos Bilal Chehab Naveen Kakarla Yang Xiang | 2022/7/20 |
Tractable Inference for Hybrid Bayesian Networks with NAT-Modeled Dynamic Discretization | The International FLAIRS Conference Proceedings | Yang Xiang Hanwen Zheng | 2022/5/4 |
Modelling, Exploration and Technology Assessment of Steep-subthreshold-slope Transistors for N5/N3 CMOS Power-performance Scaling | Yang Xiang | 2022/7/6 | |
Design enablement of CFET devices for sub-2nm CMOS nodes | Odysseas Zografos Bilal Chehab Pieter Schuddinck Gioele Mirabelli Naveen Kakarla | 2022/3/14 | |
Evaluation of BEOL scaling boosters for sub-2nm using enhanced-RO analysis | Anita Farokhnejad Simone Esposto Ivan Ciofi Odysseas Zografos Pieter Weckx | 2022/6/27 | |
Learning NAT-Modeled Bayesian Network Structures with Bayesian Approach. | Yang Xiang Wanrong Sun | 2022 | |
Self-heating in iN8–iN2 CMOS logic cells: Thermal impact of architecture (FinFET, nanosheet, forksheet and CFET) and scaling boosters | Bjorn Vermeersch Erik Bury Yang Xiang Pieter Schuddinck Krishna K Bhuwalka | 2022/6/12 | |
Earthquake-induced collapse of steel latticed shell: Energy criterion implementation and experimental validation | Engineering Structures | Zhao-Chen Zhu Yang Xiang Yun-Yong Peng Yong-Feng Luo | 2021/6/1 |
Steel frame with aseismic floor: From the viscoelastic decoupler model to the elastic structural response | Earthquake Engineering & Structural Dynamics | Yang Xiang Yuji Koetaka Kohei Nishira | 2021/5 |
Compact modeling of multidomain ferroelectric FETs: Charge trapping, channel percolation, and nucleation-growth domain dynamics | IEEE Transactions on Electron Devices | Yang Xiang M Garcia Bardon Ben Kaczer Md Nur K Alam L-Å Ragnarsson | 2021/1/26 |
Probabilistic effectiveness of visco-elastic dampers considering earthquake excitation uncertainty and ambient temperature fluctuation | Engineering Structures | Yang Xiang Hua-Rong Xie | 2021/1/1 |
Reliability and variability-aware DTCO flow: Demonstration of projections to n3 FinFET and nanosheet technologies | Gerhard Rzepa Markus Karner Oskar Baumgartner Georg Strof Franz Schanovsky | 2021/3/21 |
Co-Authors
