ProfessorsProfessors of Fudan UniversityWai-Shing Luk

Wai-Shing Luk

Fudan University

H-index: 12

Asia-China

About Wai-Shing Luk

Wai-Shing Luk, With an exceptional h-index of 12 and a recent h-index of 6 (since 2020), a distinguished researcher at Fudan University, specializes in the field of Electronic Design Automation, Design for Manufacturability, Graph Algorithm, Network Theory.

His recent articles reflect a diverse array of research interests and contributions to the field:

Iterative and Verifiable Retiming for FPGA Performance Optimization

A Fast Timing Analysis and Optimization for Latch-Based Circuits

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA

Multi-parameter Timing Optimization for Pulsed-Latch Circuits

Scalable multi-session tcp offload engine for latency-sensitive applications

Full-kv: Flexible and ultra-low-latency in-memory key-value store system design on cpu-fpga

Wai-Shing Luk Information

University	Fudan University
Position	Associate Professor of Microelectronics
Citations(all)	986
Citations(since 2020)	185
Cited By	875
hIndex(all)	12
hIndex(since 2020)	6
i10Index(all)	17
i10Index(since 2020)	4
Email	Access Email
University Profile Page	Fudan University
Google Scholar	View Google Scholar Profile

Wai-Shing Luk Skills & Research Interests

Electronic Design Automation

Design for Manufacturability

Graph Algorithm

Network Theory

Top articles of Wai-Shing Luk

Title	Journal	Author(s)	Publication Date
Iterative and Verifiable Retiming for FPGA Performance Optimization		Kaixiang Zhu Hao Zhou Wai-Shing Luk Jun Tao Lingli Wang	2023/5/8
A Fast Timing Analysis and Optimization for Latch-Based Circuits		Kaixiang Zhu Xiao Di Wai-Shing Luk Lingli Wang Jun Tao	2022/6/20
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA		Jingbo Gao Yu Qian Yihan Hu Xitian Fan Wai-Shing Luk ...	2021/12/6
Multi-parameter Timing Optimization for Pulsed-Latch Circuits		Xiao Di Wai-Shing Luk Lingli Wang	2020/11/3
Scalable multi-session tcp offload engine for latency-sensitive applications		Jingbo Gao Wenbo Yin Wai-Shing Luk Lingli Wang	2020/6/26
Full-kv: Flexible and ultra-low-latency in-memory key-value store system design on cpu-fpga	IEEE Transactions on Parallel and Distributed Systems	Yunhui Qiu Jinyu Xie Hankun Lv Wenbo Yin Wai-Shing Luk ...	2020/2/14