Shyh-Jye Jou
National Chiao Tung University
H-index: 26
Asia-Taiwan
Top articles of Shyh-Jye Jou
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter | Chung-Lun Tu Chin-Ming Chang Shyh-Jye Jou | 2023/5/21 | |
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC | Cheng-Yu Chiang Chia-Lin Hu Mark Po-Hung Lin Yu-Szu Chung Shyh-Jye Jou | 2023/1/16 | |
Method and architecture of synchronization of wireless communication system | 2023/11/21 | ||
An 1-bit by 1-bit high parallelism in-RRAM macro with co-training mechanism for DCNN applications | Chi Liu Shao-Tzu Li Tong-Lin Pan Cheng-En Ni Yun Sung | 2022/4/18 | |
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter | Shen-Zhe Lu Nai-Cheng Xue Hung-Chih Liu Chih-Wei Jen Shyh-Jye Jou | 2022/5/27 | |
DASC: a DRAM data mapping methodology for sparse convolutional neural networks | Bo-Cheng Lai Tzu-Chieh Chiang Po-Shen Kuo Wan-Ching Wang Yan-Lin Hung | 2022/3/14 | |
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique | Kang-Lun Chiu Hsun-Wei Chan Hsuan-Ping Chiu Chun-Yi Liu Chih-Wei Jen | 2022/5/27 | |
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System | Chung-Lun Tu Tse-Yuan Lin Kang-Lun Chiu Shyh-Jye Jou Pei-Yun Tsai | 2022/5/27 | |
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Henry Lopez Davila Tsung-Han Wu Shyh-Jye Jerry Jou Sau-Gee Chen Pei-Yun Tsai | 2022/11/30 |
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Yu-Hsiang Chiang Tian-Sheuan Chang Shyh Jye Jou | 2022/5/13 |
A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | Chih-Wei Jen Hung-Chih Liu Zheng-Chun Huang Nai-Cheng Xue Shyh-Jye Jerry Jou | 2022/11/7 |
Hardware-robust in-rram-computing for object detection | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | Yu-Hsiang Chiang Cheng-En Ni Yun Sung Tuo-Hung Hou Tian-Sheuan Chang | 2022/5/2 |
On Optimizing Capacitor Array Design for Advanced Node SAR ADC | Cheng-Yu Chiang Chia-Lin Hu Kang-Yu Chang Mark Po-Hung Lin Shyh-Jye Jou | 2022/6/12 | |
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO | Chia-Chen Chang Yu-Tung Chin Hossameldin A Ibrahim Kang Yu Chang Shyh-Jye Jou | 2021/5/22 | |
A reconfigurable in-SRAM computing architecture for DCNN applications | Yu-Hsien Lin Chi Liu Chia-Lin Hu Kang-Yu Chang Jia-Yin Chen | 2021/4/19 | |
Joint digital online compensation of TX and RX time-varying I/Q mismatch and DC-offset in mmWave transceiver system | IEEE Transactions on Circuits and Systems I: Regular Papers | Hung-Chih Liu Zheng-Chun Huang Ngoc-Giang Doan Chih-Wei Jen Shyh-Jye Jerry Jou | 2021/10/14 |
Robust Model Mapping Optimization For Non-Ideal Computing In-Memory | Tong-Lin Pan Shao-Tzu Li Chi Liu Tuo-Hung Hou Shyh-Jye Jou | 2021/4/19 | |
On reconfiguring memory-centric ai edge devices for cim | Hung-Ming Chen Cheng-En Ni Kang-Yu Chang Tzu-Chieh Chiang Shih-Han Chang | 2021/10/6 | |
A digital two-stage phase noise compensation and rCFO/rSCO tracking module for mmW single carrier systems | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Hsun-Wei Chan Wei-Che Lee Kang-Lun Chiu Chih-Wei Jen Shyh-Jye Jou | 2021/3/10 |
Baseband system for a wireless receiver and baseband signal processing method thereof | 2021/7/6 |
