Rinaldo Castello

Rinaldo Castello

Università degli Studi di Pavia

H-index: 49

Europe-Italy

About Rinaldo Castello

Rinaldo Castello, With an exceptional h-index of 49 and a recent h-index of 19 (since 2020), a distinguished researcher at Università degli Studi di Pavia, specializes in the field of Integrated circuits.

His recent articles reflect a diverse array of research interests and contributions to the field:

An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3

A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2 V Supply

A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing

A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology

Filtering trans-impedance amplifiers: From mW of power to GHz of bandwidth

A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter

A 17-mW 0.5–1.5-GHz bandwidth TIA based on an inductor-stabilized OTA with 35–42-dBm in-band IIP3

An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier

Rinaldo Castello Information

University

Position

Professor of Electronics Italy

Citations(all)

8197

Citations(since 2020)

1210

Cited By

7364

hIndex(all)

49

hIndex(since 2020)

19

i10Index(all)

136

i10Index(since 2020)

33

Email

University Profile Page

Università degli Studi di Pavia

Google Scholar

View Google Scholar Profile

Rinaldo Castello Skills & Research Interests

Integrated circuits

Top articles of Rinaldo Castello

Title

Journal

Author(s)

Publication Date

An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3

Simone Lecchi

Danilo Manstretta

Rinaldo Castello

2023/9/11

A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2 V Supply

Gurjeet Singh

Xhulio Selmani

Rinaldo Castello

Antonio Liscidini

2023/6/18

A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing

Xhulio Selmani

Gurjeet Singh

Rinaldo Castello

Antonio Liscidini

2023/5/21

A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology

Nicola Cordioli

Danilo Manstretta

Rinaldo Castello

2022/9/19

Filtering trans-impedance amplifiers: From mW of power to GHz of bandwidth

Nimesh Nadishka Miral

Karan Sohal

Danilo Manstretta

Rinaldo Castello

2022/4/24

A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter

IEEE Journal of Solid-State Circuits

Jin Jin

Jianhui Wu

Rinaldo Castello

Danilo Manstretta

2022/4/1

A 17-mW 0.5–1.5-GHz bandwidth TIA based on an inductor-stabilized OTA with 35–42-dBm in-band IIP3

IEEE Solid-State Circuits Letters

Nimesh Nadishka Miral

Danilo Manstretta

Rinaldo Castello

2022/2/7

An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier

Jin Jin

Simone Lecchi

Rinaldo Castello

Danilo Manstretta

2022/9/19

Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz

Rinaldo Castello

2022/9/19

A 140-μW Front-End With 5.7-dB NF and+ 10-dBm OOB-IIP3 Using Voltage-Mode Boosting Mixer

IEEE Microwave and Wireless Components Letters

Amin Mohammadpour

Danilo Manstretta

Rinaldo Castello

2021/3/17

A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter

Jin Jin

Jianhui Wu

Rinaldo Castello

Danilo Manstretta

2021/9/13

A 4.8-dB NF, 440-μW Bluetooth Receiver Front-End With a Cascode Noise Canceling LNTA

IEEE Microwave and Wireless Components Letters

Jin Jin

Jianhui Wu

Rinaldo Castello

Danilo Manstretta

2021/3/1

Design considerations for a sub-mW receiver front-end for Internet-of-Things

IEEE Open Journal of the Solid-State Circuits Society

Ehsan Kargaran

Danilo Manstretta

Rinaldo Castello

2021/9/6

A 2GS/s 10-bit Time-Interleaved Capacitive DAC for Self-Interference-Cancellation Application

Mazyar Abedinkhan Eslami

Danilo Manstretta

Rinaldo Castello

2021/7/19

A 2nd Order Current-Mode Filter with 14dB Variable Gain and 650MHz to 1GHz Tuning-Range in 28nm CMOS

Karan Sohal

Danilo Manstretta

Rinaldo Castello

2021/5/22

A highly linear SAW-less noise-canceling receiver with shared TIAs architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Mohsen Javadi

Hossein Miar-Naimi

Saheed Tijani

Danilo Manstretta

Rinaldo Castello

2021/5/13

A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz bandwidth TIA based on an inductor-stabilized OTA

Nimesh Nadishka Miral

Danilo Manstretta

Rinaldo Castello

2021/9/13

A 0.08mm2 1-6.2 GHz Receiver Front-End with Inverter-Based Shunt-Feedback Balun-LNA

Benqing Guo

Dario Prevedelli

Rinaldo Castello

Danilo Manstretta

2020/8/4

A 42-GHz TIA in 28-nm CMOS with less than 1.8% THD for optical coherent receivers

IEEE Solid-State Circuits Letters

Laura Aschei

Nicola Cordioli

Paolo Rossi

Daniele Montanari

Rinaldo Castello

...

2020/7/29

Analysis and design of a 260-MHz RF bandwidth+ 22-dBm OOB-IIP3 mixer-first receiver with third-order current-mode filtering TIA

IEEE Journal of Solid-State Circuits

Giacomo Pini

Danilo Manstretta

Rinaldo Castello

2020/4/30

See List of Professors in Rinaldo Castello University(Università degli Studi di Pavia)

Co-Authors

H-index: 169
Valerio Re

Valerio Re

Università degli Studi di Bergamo

H-index: 64
Riccardo Rovatti

Riccardo Rovatti

Università degli Studi di Bologna

H-index: 56
Andrea Baschirotto

Andrea Baschirotto

Università degli Studi di Milano-Bicocca

H-index: 41
Luca Perregrini

Luca Perregrini

Università degli Studi di Pavia

H-index: 41
Piero Malcovati

Piero Malcovati

Università degli Studi di Pavia

H-index: 38
Pietro Andreani

Pietro Andreani

Lunds Universitet

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