Peter P. Puschner

About Peter P. Puschner

Peter P. Puschner, With an exceptional h-index of 41 and a recent h-index of 16 (since 2020), a distinguished researcher at Technische Universität Wien, specializes in the field of Echtzeitsysteme, Real-Time Systems, Timing Analysis.

His recent articles reflect a diverse array of research interests and contributions to the field:

Constant-Loop Dominators for Single-Path Code Optimization

Compiler-directed constant execution time on flat memory systems

A qualitative cybersecurity analysis of time-triggered communication networks in automotive systems

The dual-path code paradigm for time-deterministic and efficient networked embedded systems

Zeitgesteuerte Kommunikationsschnittstellen in unterschiedlichen Anwendungskontexten

A processor extension for time-predictable code execution

A quantitative analysis of interfaces to time-triggered communication buses

Vicuna: a timing-predictable RISC-V vector coprocessor for scalable parallel computation

Peter P. Puschner Information

University

Position

Informatik

Citations(all)

8681

Citations(since 2020)

1542

Cited By

7732

hIndex(all)

41

hIndex(since 2020)

16

i10Index(all)

96

i10Index(since 2020)

22

Email

University Profile Page

Google Scholar

Peter P. Puschner Skills & Research Interests

Echtzeitsysteme

Real-Time Systems

Timing Analysis

Top articles of Peter P. Puschner

Title

Journal

Author(s)

Publication Date

Constant-Loop Dominators for Single-Path Code Optimization

Emad Jacob Maroun

Martin Schoeberl

Peter Puschner

2023

Compiler-directed constant execution time on flat memory systems

Emad Jacob Maroun

Martin Schoeberl

Peter Puschner

2023/5/23

A qualitative cybersecurity analysis of time-triggered communication networks in automotive systems

Journal of Systems Architecture

Raimund Kirner

Peter Puschner

2023/3/1

The dual-path code paradigm for time-deterministic and efficient networked embedded systems

Reinder J Bril

Peter Puschner

2022/12/16

Zeitgesteuerte Kommunikationsschnittstellen in unterschiedlichen Anwendungskontexten

Raimund Kirner

Peter Puschner

2022/5/25

A processor extension for time-predictable code execution

Michael Platzer

Peter Puschner

2021/6/1

A quantitative analysis of interfaces to time-triggered communication buses

IEEE/ACM Transactions on Networking

Raimund Kirner

Peter Puschner

2021/4/28

Vicuna: a timing-predictable RISC-V vector coprocessor for scalable parallel computation

Michael Platzer

Peter Puschner

2021

Timetriggered Communication Interfaces in Different Application Contexts: Zeitgesteuerte Kommunikationsschnittstellen in unterschiedlichen Anwendungskontexten

Raimund Kirner

Peter Puschner

2021/11/12

Compiling for time-predictability with dual-issue single-path code

Journal of Systems Architecture

Emad Jacob Maroun

Martin Schoeberl

Peter Puschner

2021/9/1

Synchronizing real-time tasks in time-triggered networks

Eleftherios Kyriakakis

Jens Sparsø

Peter Puschner

Martin Schoeberl

2021/6/1

A real-time application with fully predictable task timing

Michael Platzer

Peter Puschner

2020/5/19

Asynchronous vs. synchronous interfacing to time-triggered communication systems

Journal of Systems Architecture

Peter Puschner

Raimund Kirner

2020/2/1

An instruction filter for time-predictable code execution on standard processors

Michael Platzer

Peter Puschner

2020

Synchronizing real-time tasks in time-aware networks: Work-in-progress

Eleftherios Kyriakakis

Jens Sparsø

Peter Puschner

Martin Schoeberl

2020/9/20

Towards dual-issue single-path code

Emad Jacob Maroun

Martin Schoeberl

Peter Puschner

2020/5/19

See List of Professors in Peter P. Puschner University(Technische Universität Wien)