Maurizio Palesi

About Maurizio Palesi

Maurizio Palesi, With an exceptional h-index of 36 and a recent h-index of 19 (since 2020), a distinguished researcher at Università degli Studi di Catania, specializes in the field of Embedded systems, NoC, Networks on Chip.

His recent articles reflect a diverse array of research interests and contributions to the field:

Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators

Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning

A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures

Technical Program Committee Chairs

The position-based compression techniques for DNN model

Correction to: The position-based compression techniques for DNN model

A survey on deep learning hardware accelerators for heterogeneous hpc platforms

Maurizio Palesi Information

University

Position

Associate Professor Italy

Citations(all)

5011

Citations(since 2020)

1605

Cited By

4034

hIndex(all)

36

hIndex(since 2020)

19

i10Index(all)

85

i10Index(since 2020)

41

Email

University Profile Page

Google Scholar

Maurizio Palesi Skills & Research Interests

Embedded systems

NoC

Networks on Chip

Top articles of Maurizio Palesi

Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems

arXiv preprint arXiv:2404.08950

2024/4/13

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators

arXiv preprint arXiv:2210.14657

2022/10/26

Towards Fair and Firm Real-Time Scheduling in DNN Multi-Tenant Multi-Accelerator Systems via Reinforcement Learning

arXiv preprint arXiv:2403.00766

2024/2/9

Technical Program Committee Chairs

Network on Chip Architectures (NoCArc)

2023/10/28

The position-based compression techniques for DNN model

The Journal of Supercomputing

2023/10

Correction to: The position-based compression techniques for DNN model

The Journal of Supercomputing

2023/7/7

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

2023/5/21

m-BMC: Exploration of Magnetic Field Measurements for Indoor Positioning Using mini-Batch Magnetometer Calibration

2023/5/17

Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators

2023/5/15

Memory-Aware DNN Algorithm-Hardware Mapping via Integer Linear Programming

2023/5/9

Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators

IEEE Internet of Things Journal

2022/9/26

Design challenges of intra-and inter-chiplet interconnection

IEEE Design & Test

2022/8/29

Analyzing the Impact of DNN Hardware Accelerators-Oriented Compression Techniques on General-Purpose Low-End Boards

2022/8/15

Exploiting the Approximate Computing Paradigm with DNN Hardware Accelerators

2022/6/7

Combined application of approximate computing techniques in DNN hardware accelerators

2022/5/30

MEDEA: A multi-objective evolutionary approach to DNN hardware mapping

2022/3/14

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Integration

2021/11/1

On Pareto-frontier Approximate Computing for Many-core Systems

2021

See List of Professors in Maurizio Palesi University(Università degli Studi di Catania)

Co-Authors

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