Manuel E. Acacio

Manuel E. Acacio

Universidad de Murcia

H-index: 24

Europe-Spain

About Manuel E. Acacio

Manuel E. Acacio, With an exceptional h-index of 24 and a recent h-index of 8 (since 2020), a distinguished researcher at Universidad de Murcia, specializes in the field of Computer architecture, multiprocessor systems, cache coherence protocols, energy efficiency, transactional memory.

His recent articles reflect a diverse array of research interests and contributions to the field:

On the interactions between ILP and TLP with hardware transactional memory

Speculative inter-thread store-to-load forwarding in SMT architectures

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

STIFT: A spatio-temporal integrated folding tree for efficient reductions in flexible DNN accelerators

Flexagon: A multi-dataflow sparse-sparse matrix multiplication accelerator for efficient dnn processing

Analysis of the interactions between ilp and tlp with hardware transactional memory

Analysing software prefetching opportunities in hardware transactional memory

A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators

Manuel E. Acacio Information

University

Position

Professor of Computer Science ( - SPAIN)

Citations(all)

1868

Citations(since 2020)

331

Cited By

1605

hIndex(all)

24

hIndex(since 2020)

8

i10Index(all)

56

i10Index(since 2020)

8

Email

University Profile Page

Universidad de Murcia

Google Scholar

View Google Scholar Profile

Manuel E. Acacio Skills & Research Interests

Computer architecture

multiprocessor systems

cache coherence protocols

energy efficiency

transactional memory

Top articles of Manuel E. Acacio

Title

Journal

Author(s)

Publication Date

On the interactions between ILP and TLP with hardware transactional memory

Microprocessors and Microsystems

Víctor Nicolás-Conesa

Rubén Titos-Gil

Ricardo Fernández-Pascual

Alberto Ros

Manuel E Acacio

2024/2/1

Speculative inter-thread store-to-load forwarding in SMT architectures

Journal of Parallel and Distributed Computing

Josué Feliu

Alberto Ros

Manuel E Acacio

Stefanos Kaxiras

2023/3/1

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions

Sawan Singh

Josue Feliu

Manuel E Acacio

Alexandra Jimborean

Alberto Ros

2023/10/21

STIFT: A spatio-temporal integrated folding tree for efficient reductions in flexible DNN accelerators

ACM Journal on Emerging Technologies in Computing Systems

Francisco Muñoz-Martínez

José L Abellán

Manuel E Acacio

Tushar Krishna

2023/9/8

Flexagon: A multi-dataflow sparse-sparse matrix multiplication accelerator for efficient dnn processing

Francisco Muñoz-Martínez

Raveesh Garg

Michael Pellauer

José L Abellán

Manuel E Acacio

...

2023/3/25

Analysis of the interactions between ilp and tlp with hardware transactional memory

Víctor Nicolás-Conesa

Rubén Titos-Gil

Ricardo Fernández-Pascual

Alberto Ros

Manuel E Acacio

2022/3/9

Analysing software prefetching opportunities in hardware transactional memory

The Journal of Supercomputing

Marina Shimchenko

Rubén Titos-Gil

Ricardo Fernández-Pascual

Manuel E Acacio

Stefanos Kaxiras

...

2022/1

A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators

Francisco Muñoz-Martínez

José L Abellán

Manuel E Acacio

Tushar Krishna

2021/10/14

DeTraS: Delaying stores for friendly-fire mitigation in hardware transactional memory

IEEE Transactions on Parallel and Distributed Systems

Rubén Titos-Gil

Ricardo Fernández-Pascual

Alberto Ros

Manuel E Acacio

2021/5/31

A taxonomy for classification and comparison of dataflows for gnn accelerators

Raveesh Garg

Eric Qin

Francisco Muñoz Martínez

Robert Guirado

Akshay Jain

...

2021/3/1

Stonne: Enabling cycle-level microarchitectural simulation for dnn inference accelerators

Francisco Muñoz-Martínez

José L Abellán

Manuel E Acacio

Tushar Krishna

2021/11/7

ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading

Josué Feliu

Alberto Ros

Manuel E Acacio

Stefanos Kaxiras

2021/10/18

CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators

Francisco Muñoz-Martínez

José L Abellán

Manuel E Acacio

2020

2019 Index IEEE Transactions on Parallel and Distributed Systems Vol. 30

IEEE Transactions on Parallel and Distributed Systems

C Ababei

D Abbasinezhad-Mood

A Abdi

N Abubaker

ME Acacio

...

2020/1

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory

Journal of Parallel and Distributed Computing

Rubén Titos-Gil

Ricardo Fernández-Pascual

Alberto Ros

Manuel E Acacio

2020/11/1

STONNE: A detailed architectural simulator for flexible neural network accelerators

arXiv preprint arXiv:2006.07137

Francisco Muñoz-Martínez

José L Abellán

Manuel E Acacio

Tushar Krishna

2020/6/10

See List of Professors in Manuel E. Acacio University(Universidad de Murcia)