Luis Piñuel

About Luis Piñuel

Luis Piñuel, With an exceptional h-index of 19 and a recent h-index of 8 (since 2020), a distinguished researcher at Universidad Complutense de Madrid, specializes in the field of Computer Architecture, Embedded Systems, Compilers.

His recent articles reflect a diverse array of research interests and contributions to the field:

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

Improving the representativeness of simulation intervals for the cache memory system

PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem

PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core

Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors

SUPERSONIC-V: deSarrollo de entornos virtUales Para dEspliegue de haRdware baSadO eN rIsC-V

RVfpga: Computer Architecture Course and MOOC Using a RISC-V SoC Targeted to an FPGA and Simulation

Customizing the CVA6 RISC-V core to integrate posit and quire instructions

Luis Piñuel Information

University

Position

Associate Professor

Citations(all)

1014

Citations(since 2020)

218

Cited By

867

hIndex(all)

19

hIndex(since 2020)

8

i10Index(all)

31

i10Index(since 2020)

6

Email

University Profile Page

Google Scholar

Luis Piñuel Skills & Research Interests

Computer Architecture

Embedded Systems

Compilers

Top articles of Luis Piñuel

Title

Journal

Author(s)

Publication Date

Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

IEEE Transactions on Circuits and Systems II: Express Briefs

José L Imaña

Luis Piñuel

Yao-Ming Kuo

Oscar Ruano

Francisco García-Herrero

2024/2/23

Improving the representativeness of simulation intervals for the cache memory system

Ieee Access

Nicolas Bueno

Fernando Castro

Luis Pinuel

Jose I Gomez-Perez

Francky Catthoor

2024/1/8

PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem

David Mallasén

Raul Murillo

Alberto A Del Barrio

Guillermo Botella

Luis Piñuel

...

2023/6/6

PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core

David Mallasén

Raul Murillo

Alberto A Del Barrio

Guillermo Botella

Luis Piñuel

...

2023/5/9

Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors

Francisco Igual

Luis Piñuel

Sandra Catalán

Héctor Martínez

Adrián Castelló

...

2023/11/12

SUPERSONIC-V: deSarrollo de entornos virtUales Para dEspliegue de haRdware baSadO eN rIsC-V

Alberto Antonio del Barrio García

Guillermo Botella Juan

Luis Piñuel Moreno

Carlos Roa Romero

Raúl Murillo Montero

...

2023/7/14

RVfpga: Computer Architecture Course and MOOC Using a RISC-V SoC Targeted to an FPGA and Simulation

Daniel Chaver Martinez

Sarah L Harris

Luis Piñuel

Olof Kindgren

Robert CW Owen

2023/6/25

Customizing the CVA6 RISC-V core to integrate posit and quire instructions

David Mallasén

Raul Murillo

Alberto A Del Barrio

Guillermo Botella

Luis Piñuel

...

2022/11/16

PERCIVAL: Open-source posit RISC-V core with quire capability

IEEE Transactions on Emerging Topics in Computing

David Mallasén

Raul Murillo

Alberto A Del Barrio

Guillermo Botella

Luis Piñuel

...

2022/7/6

Spatio-temporal resolution of irradiance samples in machine learning approaches for irradiance forecasting

IEEE Access

Annette Eschenbach

Guillermo Yepes

Christian Tenllado

Jose I Gomez-Perez

Luis Pinuel

...

2020/3/13

Estructura de Computadores. Manual de Laboratorio.

Christian Tenllado van der Reijden

Luis Piñuel Moreno

2020

Benchmarking performance and power of USB accelerators for inference with MLPerf

Leandro Ariel Libutti

Francisco D Igual

Luis Pinuel

Laura De Giusti

Marcelo Naiouf

2020/1

Towards a malleable tensorflow implementation

Leandro Ariel Libutti

Francisco D Igual

Luis Piñuel

Laura De Giusti

Marcelo Naiouf

2020/9/8

See List of Professors in Luis Piñuel University(Universidad Complutense de Madrid)