Jose Flich

About Jose Flich

Jose Flich, With an exceptional h-index of 36 and a recent h-index of 15 (since 2020), a distinguished researcher at Universidad Politécnica de València, specializes in the field of Computer Architecture, on-chip communication.

His recent articles reflect a diverse array of research interests and contributions to the field:

Toward matrix multiplication for deep learning inference on the Xilinx Versal

An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration

HPC Platform for Railway Safety-Critical Functionalities Based on Artificial Intelligence

GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips

Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms

The SELENE deep learning acceleration framework for safety-related applications

Efficient inference of image-based neural network models in reconfigurable systems with pruning and quantization

Jose Flich Information

University

Position

Associate Professor

Citations(all)

4202

Citations(since 2020)

737

Cited By

3856

hIndex(all)

36

hIndex(since 2020)

15

i10Index(all)

100

i10Index(since 2020)

25

Email

University Profile Page

Universidad Politécnica de València

Google Scholar

View Google Scholar Profile

Jose Flich Skills & Research Interests

Computer Architecture

on-chip communication

Top articles of Jose Flich

Title

Journal

Author(s)

Publication Date

Toward matrix multiplication for deep learning inference on the Xilinx Versal

Jie Lei

José Flich

Enrique S Quintana-Ortí

2023/3/1

An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration

Rafael Tornero

David Rodríguez

José M Martínez

José Flich

2023/11/15

HPC Platform for Railway Safety-Critical Functionalities Based on Artificial Intelligence

Mikel Labayen Esnaola

Laura Medina

Fernando Eizaguirre

José Flich

Naiara Aginako Bengoa

2023/8/7

GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal

Jie Lei

Héctor Martínez

José Flich

Enrique S Quintana-Ortí

2023/5/21

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips

Xabier Iturbe

Nassim Abderrahmane

Jaume Abella

Sergi Alcaide

Eric Beyne

...

2023/4/17

Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms

David Rodríguez Agut

Rafael Tornero

Josè Flich

2023/4/17

The SELENE deep learning acceleration framework for safety-related applications

Laura Medina

Salva Carrion

Pablo Andreu

Tomas Picornell

Jose Flich

...

2022/3/14

Efficient inference of image-based neural network models in reconfigurable systems with pruning and quantization

José Flich

Laura Medina

Izan Catalán

Carles Hernández

Andrea Bragagnolo

...

2022/10/16

The DeepHealth HPC Infrastructure: Leveraging Heterogenous HPC and Cloud-Computing Infrastructures for IA-Based Medical Solutions

Eduardo Quiñones

Jesus Perales

Jorge Ejarque

Asaf Badouh

Santiago Marco

...

2022/1/13

Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence

Future generation computer systems

Jorge Ejarque

Rosa M Badia

Loïc Albertin

Giovanni Aloisio

Enrico Baglione

...

2022/9/1

Application-Specific Mapping Optimizations for Photonic Networks-on-Chip

Edoardo Fusella

Alessandro Cilardo

José Flich

2022/9/1

The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures

Marco Aldinucci

David Atienza

Federico Bolelli

Mónica Caballero

Iacopo Colonnelli

...

2022/4/29

Improving the robustness of redundant execution with register file randomization

Ilya Tuzov

Pablo Andreu

Laura Medina

Tomas Picornell

Antonio Robles

...

2021/11/1

UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility

The Journal of Supercomputing

Juan-José Crespo

José L Sánchez

Francisco J Alfaro-Cortés

José Flich

José Duato

2021/11

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience

José Flich

Rafael Tornero

David Rodriguez

Davide Russo

José Maria Martínez

...

2021/2/1

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

IEEE Access

Tomás Picornell

Jose Flich

Duato Jose

Carles Hernández

2020/10/26

TDSR: Transparent Distributed Segment-Based Routing

arXiv preprint arXiv:2006.04549

Juan-Jose Crespo

German Maglione-Mathey

José L Sánchez

Francisco J Alfaro-Cortés

José Flich

2020/6/4

Enforcing predictability of many-cores with DCFNoC

IEEE Transactions on Computers

Tomas Picornell

José Flich

Carles Hernández

Jose Duato

2020/4/15

Distributed Training on a Highly Heterogeneous HPC System

Jose Flich

Carles Hernandez

Eduardo Quiñones

Roberto Paredes

2020

See List of Professors in Jose Flich University(Universidad Politécnica de València)

Co-Authors

H-index: 54
Pasi Liljeberg

Pasi Liljeberg

Turun yliopisto

H-index: 53
Juan-Carlos Cano Escribá (ORCID:0000-0002-0038-0539)

Juan-Carlos Cano Escribá (ORCID:0000-0002-0038-0539)

Universidad Politécnica de València

H-index: 42
Juha Plosila

Juha Plosila

Turun yliopisto

H-index: 36
Maurizio Palesi

Maurizio Palesi

Università degli Studi di Catania

H-index: 35
Masoud Daneshtalab

Masoud Daneshtalab

Mälardalens högskola

H-index: 30
Federico Silla

Federico Silla

Universidad Politécnica de València

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