Joerg Appenzeller

Joerg Appenzeller

Purdue University

H-index: 72

North America-United States

About Joerg Appenzeller

Joerg Appenzeller, With an exceptional h-index of 72 and a recent h-index of 44 (since 2020), a distinguished researcher at Purdue University, specializes in the field of nanoelectronics.

His recent articles reflect a diverse array of research interests and contributions to the field:

Reliability of High-Performance Monolayer MoS2 Transistors on Scaled High-κ HfO2

Unconventional Spin Hall Effect in Low Symmetry Semimetal for Large Spin-Orbit Readout Unit

Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS FETs

Tailoring Amorphous Boron Nitride for High-Performance 2D Electronics

Wafer-scale CVD Monolayer WSe2 p-FETs with Record-high 727 μA/μm Ion and 490 μS/ μm gmax via Hybrid Charge Transfer and Molecular Doping

A magnetoelectric memory device based on pseudo-magnetization

A mobility study of monolayer MoS2 on low-κ/high-κ dielectrics

High-Performance Complementary Circuits from Two-Dimensional MoTe2

Joerg Appenzeller Information

University

Position

Professor of Electrical and Computer Engineering

Citations(all)

29507

Citations(since 2020)

7458

Cited By

24701

hIndex(all)

72

hIndex(since 2020)

44

i10Index(all)

187

i10Index(since 2020)

108

Email

University Profile Page

Purdue University

Google Scholar

View Google Scholar Profile

Joerg Appenzeller Skills & Research Interests

nanoelectronics

Top articles of Joerg Appenzeller

Title

Journal

Author(s)

Publication Date

Reliability of High-Performance Monolayer MoS2 Transistors on Scaled High-κ HfO2

Zhihong Chen

Hao-Yu Lan

Shao-Heng Yang

Rahul Tripathi

Joerg Appenzeller

2024/4/1

Unconventional Spin Hall Effect in Low Symmetry Semimetal for Large Spin-Orbit Readout Unit

Bulletin of the American Physical Society

Rahul Tripathi

Hao-Yu Lan

Punyashloka Debashis

Hai Li

Mahendra DC

...

2024/3/6

Experimental demonstration of an integrated on-chip p-bit core utilizing stochastic Magnetic Tunnel Junctions and 2D-MoS FETs

arXiv preprint arXiv:2308.10989

John Daniel

Zheng Sun

Xuejian Zhang

Yuanqiu Tan

Neil Dilley

...

2023/8/21

Tailoring Amorphous Boron Nitride for High-Performance 2D Electronics

arXiv preprint arXiv:2312.09136

Cindy Y Chen

Zheng Sun

Riccardo Torsi

Ke Wang

Jessica Kachian

...

2023/12/14

Wafer-scale CVD Monolayer WSe2 p-FETs with Record-high 727 μA/μm Ion and 490 μS/ μm gmax via Hybrid Charge Transfer and Molecular Doping

Hao-Yu Lan

Rahul Tripathi

Xiangkai Liu

Joerg Appenzeller

Zhihong Chen

2023/12/9

A magnetoelectric memory device based on pseudo-magnetization

Journal of Applied Physics

Tingting Shen

Orchi Hassan

Neil R Dilley

Supriyo Datta

Kerem Y Camsari

...

2023/7/21

A mobility study of monolayer MoS2 on low-κ/high-κ dielectrics

Zheng Sun

Cindy Chen

Joshua A Robinson

Zhihong Chen

Joerg Appenzeller

2023/6/25

High-Performance Complementary Circuits from Two-Dimensional MoTe2

Nano Letters

Jun Cai

Zheng Sun

Peng Wu

Rahul Tripathi

Hao-Yu Lan

...

2023/11/17

Dielectric Interface Engineering for High-Performance Monolayer MoS2 Transistors via TaOxInterfacial Layer

IEEE Transactions on Electron Devices

Hao-Yu Lan

Vladimir P Oleshko

Albert V Davydov

Joerg Appenzeller

Zhihong Chen

2023/3/13

Cross-coupled gated tunnel diode (xtd) device with increased peak-to-valley current ratio (pvcr)

2023/9/14

Design and Process Co-Optimization of 2-D Monolayer Transistors via Machine Learning

IEEE Transactions on Electron Devices

Chin-Cheng Chiang

Hao-Yu Lan

Lina Liu

Yong P Chen

Dmitry Zemlyanov

...

2023/9/12

Electric field control of interaction between magnons and quantum spin defects

Physical Review Research

Abhishek B Solanki

Simeon I Bogdanov

Mohammad M Rahman

Avinash Rustagi

Neil R Dilley

...

2022/2/23

Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS2

ACS nano

Zheng Sun

Chin-Sheng Pang

Peng Wu

Terry YT Hung

Ming-Yang Li

...

2022/9/12

Explaining Steep-Slope Switching in Carbon Nanotube Dirac-Source Field-Effect Transistors

IEEE Transactions on Electron Devices

Peng Wu

Joerg Appenzeller

2022/7/13

Design considerations for 2-D Dirac-source FETs—Part I: Basic operation and device parameters

IEEE Transactions on Electron Devices

Peng Wu

Joerg Appenzeller

2022/6/17

2022 Index Electron Device Letters Vol. 43

IEEE Electron Device Letters

KA Aabrar

T Abbey

S Abdulazhanov

C Adelmann

MM Afandi

...

2022/12

Design Considerations for 2D Dirac-Source FETs: Device Parameters, Non-Idealities and Benchmarking

arXiv preprint arXiv:2203.11248

Peng Wu

Joerg Appenzeller

2022/3/21

Cross-coupled gated tunneling diodes with unprecedented PVCRs enabling compact SRAM design—Part II: SRAM circuit

IEEE Transactions on Electron Devices

Mengyuan Li

Peng Wu

Bo Zhou

Joerg Appenzeller

Xiaobo Sharon Hu

2022/9/29

Two-dimensional transistors with reconfigurable polarities for secure circuits

NATURE electronics

Peng Wu

Dayane Reis

Xiaobo Sharon Hu

Joerg Appenzeller

2021/1

Air-Stable P-Doping in Record High-Performance Monolayer WSe2 Devices

IEEE Electron Device Letters

Chin-Cheng Chiang

Hao-Yu Lan

Chin-Sheng Pang

Joerg Appenzeller

Zhihong Chen

2021/12/13

See List of Professors in Joerg Appenzeller University(Purdue University)

Co-Authors

H-index: 74
Gerhard Klimeck

Gerhard Klimeck

Purdue University

H-index: 67
Richard Martel

Richard Martel

Université de Montréal

H-index: 47
Zhihong Chen

Zhihong Chen

Purdue University

H-index: 45
Saptarshi Das

Saptarshi Das

Penn State University

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