Jatindra Kumar Deka

About Jatindra Kumar Deka

Jatindra Kumar Deka, With an exceptional h-index of 13 and a recent h-index of 9 (since 2020), a distinguished researcher at Indian Institute of Technology Guwahati,

His recent articles reflect a diverse array of research interests and contributions to the field:

Incomplete Testing of SOC

Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT

Retesting defective circuits to allow acceptable faults for yield enhancement

Selective fault-masking for improving yield and performance of on-chip networks

ATPG for Incomplete Testing of SOC Considering Bridging Faults

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels

Improving reliability in spidergon network on chip-microprocessors

Approximate testing of digital VLSI circuits using error significance based fault analysis

Jatindra Kumar Deka Information

University

Position

Professor CSE Department

Citations(all)

972

Citations(since 2020)

608

Cited By

579

hIndex(all)

13

hIndex(since 2020)

9

i10Index(all)

22

i10Index(since 2020)

8

Email

University Profile Page

Indian Institute of Technology Guwahati

Google Scholar

View Google Scholar Profile

Top articles of Jatindra Kumar Deka

Title

Journal

Author(s)

Publication Date

Incomplete Testing of SOC

Journal of Electronic Testing

Kunwer Mrityunjay Singh

Jatindra Deka

Santosh Biswas

2023/6

Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT

Nanu Alan Kachari

Santosh Biswas

Jatindra Kumar Deka

2021/12/5

Retesting defective circuits to allow acceptable faults for yield enhancement

Journal of Electronic Testing

Sisir Kumar Jena

Santosh Biswas

Jatindra Kumar Deka

2021/12

Selective fault-masking for improving yield and performance of on-chip networks

Biswajit Bhowmik

Jatindra Kumar Deka

Santosh Biswas

2021/10/17

ATPG for Incomplete Testing of SOC Considering Bridging Faults

Kunwer Mrityunjay Singh

Santosh Biswas

Jatindra Kumar Deka

2021/12/7

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels

Biswajit Bhowmik

Santosh Biswas

Jatindra Kumar Deka

2020/10/11

Improving reliability in spidergon network on chip-microprocessors

Biswajit Bhowmik

Jatindra Kumar Deka

Santosh Biswas

2020/8/9

Approximate testing of digital VLSI circuits using error significance based fault analysis

Sisir Kumar Jena

Santosh Biswas

Jatindra Kumar Deka

2020/7/23

Locating open-channels in octagon networks on chip-microprocessors

Biswajit Bhowmik

Santosh Biswas

Jatindra Kumar Deka

Bhargab B Bhattacharya

2020/7/6

Reliability monitoring in a smart noc component

Biswajit Bhowmik

Jatindra Kumar Deka

Santosh Biswas

2020/11/23

Maximizing yield through retesting of rejected circuits using approximation technique

Sisir Kumar Jena

Santosh Biswas

Jatindra Kumar Deka

2020/11/16

See List of Professors in Jatindra Kumar Deka University(Indian Institute of Technology Guwahati)