Jae-sun Seo

Jae-sun Seo

Arizona State University

H-index: 42

North America-United States

About Jae-sun Seo

Jae-sun Seo, With an exceptional h-index of 42 and a recent h-index of 37 (since 2020), a distinguished researcher at Arizona State University, specializes in the field of VLSI / ASIC, Digital/Mixed-Signal Circuits, FPGA, ML Hardware Design, Neuromorphic Computing.

His recent articles reflect a diverse array of research interests and contributions to the field:

Patch-based Selection and Refinement for Early Object Detection

PS-IMC: A 2385.7 TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs

Transformer-Based Selective Super-resolution for Efficient Image Refinement

Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training

Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”

A Dynamic Power-Only Compute-In-Memory Macro With Power-of-Two Nonlinear SAR ADC for Non-Volatile Ferroelectric Capacitive Crossbar Array

Method and system for a temperature-resilient neural network training model

Exploiting 2.5 D/3D Heterogeneous Integration for AI Computing

Jae-sun Seo Information

University

Position

___

Citations(all)

7912

Citations(since 2020)

6375

Cited By

3758

hIndex(all)

42

hIndex(since 2020)

37

i10Index(all)

118

i10Index(since 2020)

101

Email

University Profile Page

Arizona State University

Google Scholar

View Google Scholar Profile

Jae-sun Seo Skills & Research Interests

VLSI / ASIC

Digital/Mixed-Signal Circuits

FPGA

ML Hardware Design

Neuromorphic Computing

Top articles of Jae-sun Seo

Title

Journal

Author(s)

Publication Date

Patch-based Selection and Refinement for Early Object Detection

Tianyi Zhang

Kishore Kasichainula

Yaoxin Zhuo

Baoxin Li

Jae-Sun Seo

...

2024

PS-IMC: A 2385.7 TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs

IEEE Solid-State Circuits Letters

Amitesh Sridharan

Jyotishman Saikia

Fan Zhang

Jae-sun Seo

Deliang Fan

2024/2/23

Transformer-Based Selective Super-resolution for Efficient Image Refinement

Proceedings of the AAAI Conference on Artificial Intelligence

Tianyi Zhang

Kishore Kasichainula

Yaoxin Zhuo

Baoxin Li

Jae-Sun Seo

...

2024/3/24

Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training

Advances in Neural Information Processing Systems

Jian Meng

Li Yang

Kyungmin Lee

Jinwoo Shin

Deliang Fan

...

2024/2/13

Corrections to “A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array”

IEEE Solid-State Circuits Letters

Injune Yeo

Wangxin He

Yuan-Chun Luo

Shimeng Yu

Jae-Sun Seo

2024/3/21

A Dynamic Power-Only Compute-In-Memory Macro With Power-of-Two Nonlinear SAR ADC for Non-Volatile Ferroelectric Capacitive Crossbar Array

IEEE Solid-State Circuits Letters

Injune Yeo

Wangxin He

Yuan-Chun Luo

Shimeng Yu

Jae-sun Seo

2024/2/1

Method and system for a temperature-resilient neural network training model

2024/3/21

Exploiting 2.5 D/3D Heterogeneous Integration for AI Computing

Zhenyu Wang

Jingbo Sun

Alper Goksoy

Sumit K Mandal

Yaotian Liu

...

2024/1/22

3D In-Sensor Computing for Real-Time DVS Data Compression: 65nm Hardware-Algorithm Co-Design

IEEE Solid-State Circuits Letters

Gopikrishnan R Nair

Pragnya S Nalla

Gokul Krishnan

Jonghyun Oh

Ahmed Hassan

...

2024/3/8

High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design

ACM Transactions on Reconfigurable Technology and Systems

Anupreetham Anupreetham

Mohamed Ibrahim

Mathew Hall

Andrew Boutros

Ajay Kuzhively

...

2024/1/15

11. A. Hannun et al.,“Sequence-to-sequence speech recognition with time-depth separable convolutions,”

IEEE Micro

JAESUN SEO

2024/3

System and method for learning sparse features for self-supervised learning with contrastive dual gating

2024/4/25

System and method for robust neural networking via noise injection

2023/3/16

Prive: Efficient rram programming with chip verification for rram-based in-memory computing acceleration

Wangxin He

Jian Meng

Sujan Kumar Gonugondla

Shimeng Yu

Naresh R Shanbhag

...

2023/4/17

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity

IEEE Journal of Solid-State Circuits

Shreyas Kolala Venkataramanaiah

Jian Meng

Han-Sok Suh

Injune Yeo

Jyotishman Saikia

...

2023/5/15

Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators

Jae-Sun Seo

2023/7/9

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro

Jyotishman Saikia

Amitesh Sridharan

Injune Yeo

Shreyas Venkataramanaiah

Deliang Fan

...

2023/9/11

SRAM In-Memory Computing Macro With Delta-Sigma Modulator Based Variable-Resolution Activation

IEEE Solid-State Circuits Letters

Vasundhara Damodaran

Ziyu Liu

Jian Meng

Jae-sun Seo

Arindam Sanyal

2023/10/24

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

IEEE Transactions on NanoBioscience

Jin-Woo Kim

Jangho Kim

Deok-Ho Kim

2016/12

Resistive random-access memory for exclusive nor (xnor) neural networks

2023/3/9

See List of Professors in Jae-sun Seo University(Arizona State University)