Eduardo de la Torre

Eduardo de la Torre

Universidad Politécnica de Madrid

H-index: 25

Europe-Spain

About Eduardo de la Torre

Eduardo de la Torre, With an exceptional h-index of 25 and a recent h-index of 15 (since 2020), a distinguished researcher at Universidad Politécnica de Madrid, specializes in the field of FPGAs, Reconfigurable systems, Evolvable hardware, Sensor networks, digital signal processing.

His recent articles reflect a diverse array of research interests and contributions to the field:

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays

A multi-FPGA scalable framework for deep reinforcement learning through neuroevolution

Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)

Run-time monitoring and ml-based modeling in reconfigurable multi-accelerator systems

Exploiting hardware-based data-parallel and multithreading models for smart edge computing in reconfigurable FPGAs

Eduardo de la Torre Information

University

Position

___

Citations(all)

2097

Citations(since 2020)

712

Cited By

1629

hIndex(all)

25

hIndex(since 2020)

15

i10Index(all)

56

i10Index(since 2020)

21

Email

University Profile Page

Universidad Politécnica de Madrid

Google Scholar

View Google Scholar Profile

Eduardo de la Torre Skills & Research Interests

FPGAs

Reconfigurable systems

Evolvable hardware

Sensor networks

digital signal processing

Top articles of Eduardo de la Torre

Title

Journal

Author(s)

Publication Date

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads

Microprocessors and Microsystems

Juan Encinas

Alfonso Rodríguez

Andrés Otero

Eduardo de la Torre

2024/4/9

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Microprocessors and Microsystems

Jose Nunez-Yanez

Andres Otero

Eduardo de la Torre

2023/4/1

Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning

Andrés Otero

Guillermo Sanllorente

Eduardo de la Torre

Jose Nunez-Yanez

2023/9/16

Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays

Daniel Vázquez

Alfonso Rodríguez

Andrés Otero

Eduardo de la Torre

2022/11/16

A multi-FPGA scalable framework for deep reinforcement learning through neuroevolution

Javier Laserna

Andrés Otero

Eduardo de la Torre

2022/9/19

Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)

Rafael Zamacola

Andrés Otero

Alfonso Rodríguez

Eduardo de la Torre

2022

Run-time monitoring and ml-based modeling in reconfigurable multi-accelerator systems

Juan Encinas

Alfonso Rodríguez

Andrés Otero

Eduardo De La Torre

2021/11/24

Exploiting hardware-based data-parallel and multithreading models for smart edge computing in reconfigurable FPGAs

IEEE Transactions on Computers

Alfonso Rodríguez

Andrés Otero

Marco Platzner

Eduardo de la Torre

2021/8/27

Multi-grain reconfigurable and scalable overlays for hardware accelerator composition

Journal of Systems Architecture

Rafael Zamacola

Andres Otero

Eduardo de la Torre

2021/12/1

Exploiting multi-level parallelism for run-time adaptive inverse kinematics on heterogeneous mpsocs

IEEE Access

Leonardo Suriano

Andrés Otero

Alfonso Rodríguez

Manuel Sánchez-Renedo

Eduardo De La Torre

2020/6/26

A dynamically reconfigurable BbNN architecture for scalable neuroevolution in hardware

Electronics

Alberto García

Rafael Zamacola

Andrés Otero

Eduardo de la Torre

2020/5/13

Run-time reconfigurable MPSoC-based on-board processor for vision-based space navigation

IEEE Access

Arturo Pérez

Alfonso Rodríguez

Andrés Otero

David González Arjona

Álvaro Jiménez-Peralo

...

2020/3/25

An integrated approach and tool support for the design of fpga-based multi-grain reconfigurable systems

IEEE Access

Rafael Zamacola

Andrés Otero

Alberto García

Eduardo De La Torre

2020/11/6

Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems

Alberto Ortiz

Rafael Zamacola

Alfonso Rodríguez

Andrés Otero

Eduardo de la Torre

2020/3/25

Lossy hyperspectral image compression on a reconfigurable and fault-tolerant fpga-based adaptive computing platform

Electronics

Yubal Barrios

Alfonso Rodríguez

Antonio Sánchez

Arturo Pérez

Sebastián López

...

2020/10

Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs

Leonardo Suriano

David Lima

Eduardo de la Torre

2020

A machine-learning-based distributed system for fault diagnosis with scalable detection quality in industrial IoT

IEEE Internet of Things Journal

Rodrigo Marino

Cristian Wisultschew

Andrés Otero

Jose M Lanza-Gutierrez

Jorge Portilla

...

2020/9/23

See List of Professors in Eduardo de la Torre University(Universidad Politécnica de Madrid)

Co-Authors

H-index: 50
Javier Uceda

Javier Uceda

Universidad Politécnica de Madrid

H-index: 38
Lukas Sekanina

Lukas Sekanina

Vysoké ucení technické v Brne

H-index: 31
Roberto Sarmiento

Roberto Sarmiento

Universidad de Las Palmas de Gran Canaria

H-index: 28
Teresa Riesgo

Teresa Riesgo

Universidad Politécnica de Madrid

H-index: 25
Sebastian Lopez

Sebastian Lopez

Universidad de Las Palmas de Gran Canaria

H-index: 23
Angel de Castro

Angel de Castro

Universidad Autónoma de Madrid

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