Davide Rossi
Università degli Studi di Bologna
H-index: 36
Europe-Italy
Top articles of Davide Rossi
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation | International Journal of Parallel Programming | Alessandro Ottaviano Robert Balas Giovanni Bambini Antonio Del Vecchio Maicol Ciani | 2024/2/26 |
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation | IEEE Transactions on Circuits and Systems I: Regular Papers | Luca Valente Alessandro Nadalini Asif Hussain Chiralil Veeran Mattia Sinigaglia Bruno Sá | 2024/2/7 |
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS | Moritz Scherer Manuel Eggimann Alfio Di Mauro Arpan Suravi Prasad Francesco Conti | 2023/9/11 | |
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Jie Chen Igor Loi Eric Flamand Giuseppe Tagliavini Luca Benini | 2023/2/20 |
Cyber security aboard micro aerial vehicles: An opentitan-based visual communication use case | Maicol Ciani Stefano Bonato Rafail Psiakis Angelo Garofalo Luca Valente | 2023/5/21 | |
Reducing Load-Use dependency-induced performance penalty in the Open-Source RISC-V CVA6 CPU | Gianmarco Ottavi Florian Zaruba Luca Benini Davide Rossi | 2023/9/6 | |
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC | Luca Valente Yvan Tortorella Mattia Sinigaglia Giuseppe Tagliavini Alessandro Capotondi | 2023/4/17 | |
22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing | Francesco Conti Davide Rossi Gianna Paulin Angelo Garofalo Alfio Di Mauro | 2023/2/19 | |
CVA6 RISC-V virtualization: Architecture, microarchitecture, and design space exploration | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Bruno Sá Luca Valente José Martins Davide Rossi Luca Benini | 2023/8/28 |
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes | Seyed Ahmad Mirsalari Giuseppe Tagliavini Davide Rossi Luca Benini | 2023/4/17 | |
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs | Luca Valente Asif Veeran Mattia Sinigaglia Yvan Tortorella Alessandro Nadalini | 2023 | |
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge | Vikram Jain Matheus Cavalcante Nazareno Bruschi Michael Rogenmoser Thomas Benz | 2023/7/9 | |
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration | Future Generation Computer Systems | Yvan Tortorella Luca Bertaccini Luca Benini Davide Rossi Francesco Conti | 2023/12/1 |
End-to-end DNN inference on a massively parallel analog in memory computing architecture | Nazareno Bruschi Giuseppe Tagliavini Angelo Garofalo Francesco Conti Irem Boybat | 2023/4/17 | |
A 3 tops/w risc-v parallel cluster for inference of fine-grain mixed-precision quantized neural networks | Alessandro Nadalini Georg Rutishauser Alessio Burrello Nazareno Bruschi Angelo Garofalo | 2023/6/20 | |
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing | IEEE Journal of Solid-State Circuits | Francesco Conti Gianna Paulin Angelo Garofalo Davide Rossi Alfio Di Mauro | 2023/10/3 |
Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode | IEEE Transactions on Circuits and Systems I: Regular Papers | Gianmarco Ottavi Angelo Garofalo Giuseppe Tagliavini Francesco Conti Alfio Di Mauro | 2023/3/15 |
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays | Mattia Sinigaglia Luca Bertaccini Luca Valente Angelo Garofalo Simone Benatti | 2023/5/21 | |
Darkside: 2.6 GFLOPS, 8.7 mW heterogeneous RISC-V cluster for extreme-edge on-chip DNN inference and training | Angelo Garofalo Matteo Perotti Luca Valente Yvan Tortorella Alessandro Nadalini | 2022/9/19 | |
A heterogeneous in-memory computing cluster for flexible end-to-end inference of real-world deep neural networks | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | Angelo Garofalo Gianmarco Ottavi Francesco Conti Geethan Karunaratne Irem Boybat | 2022/4/28 |
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