CHIRN CHYE BOON
Nanyang Technological University
H-index: 32
Asia-Singapore
Top articles of CHIRN CHYE BOON
Title | Journal | Author(s) | Publication Date |
|---|---|---|---|
A 28.8-to-43.2 GHz 79.8 fs Jitter and 78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration | IEEE Transactions on Microwave Theory and Techniques | Yuan Liang Chirn Chye Boon Chenyang Li Qian Chen | 2024/2/27 |
Select your blocker | B VEERA REDDY | ||
A 2.4 dB NF+ 4.1 dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration | Zhe Liu Chirn Chye Boon Yangtao Dong Kaituo Yang | 2023/9/11 | |
A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression | IEEE Transactions on Microwave Theory and Techniques | Yangtao Dong Chirn Chye Boon Zhe Liu Kaituo Yang | 2023/6/22 |
A 14.2 mW 29-39.3-GHz Two-Stage PLL with a Current-Reuse Coupled Mixer Phase Detector | Yuan Liang Chirn Chye Boon Qian Chen | 2023/6/11 | |
17.8 A Single-Channel 10GS/s 8b> 36.4 d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS | Qian Chen Yuan Liang Chirn Chye Boon Qing Liu | 2023/2/19 | |
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with+ 10dBm in-Band IIP3 in Current-Mode and 1.7 dB NF in Voltage-Mode | Kaituo Yang Chirn Chye Boon Zhe Liu Jiaming Piao Ting Guo | 2022/2/20 | |
A 2-GHz dual-path sub-sampling PLL with ring VCO phase noise suppression | Yangtao Dong Chirn Chye Boon Kaituo Yang Zhe Liu | 2022/4/24 | |
A 2-mW 0.3-to-1GHz Wide-Injection-Locking Multi-mode Transmitter with a 1-Mb/s Data Rate | Yong Chen Yushi Zhou Chirn Chye Boon Pui-In Mak Rui P Martins | 2022/9/23 | |
A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector | IEEE Transactions on Microwave Theory and Techniques | Yuan Liang Chirn Chye Boon | 2022/2/18 |
Apparatus and method for wireless communication | 2022/4/12 | ||
A 0.6 V 4 GS/s− 56.4 dB THD voltage-to-time converter in 28 nm CMOS | IEEE Access | Qian Chen Chirn Chye Boon Yuan Liang | 2022/8/22 |
High voltage logic circuit | 2022/8/9 | ||
A 23.4 mW− 72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector | IEEE Microwave and Wireless Components Letters | Yuan Liang Chirn Chye Boon Qian Chen | 2022/3/25 |
An equivalent-time sampling millimeter-wave ultra-wideband radar pulse digitizer in CMOS | IEEE Transactions on Circuits and Systems I: Regular Papers | Gibran Limi Jaya Chirn Chye Boon Shoushun Chen Liter Siek | 2022/7/20 |
A low-jitter and low-reference-spur 320 GHz signal source with an 80 GHz integer-N phase-locked loop using a quadrature XOR technique | IEEE Transactions on Microwave Theory and Techniques | Yuan Liang Chirn Chye Boon Gengzhen Qi Giannino Dziallas Dietmar Kissinger | 2022/3/22 |
A 0.092-mm2 2–12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction | IEEE Transactions on Circuits and Systems II: Express Briefs | Zhe Liu Chirn Chye Boon | 2022/6/22 |
A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Boosting | Zhe Liu Chirn Chye Boon Chenyang Li Kaituo Yang Yangtao Dong | 2022/2/20 | |
A Single-Channel Voltage-Scalable 8-GS/s 8-b 37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS | IEEE Journal of Solid-State Circuits | Qian Chen Chirn Chye Boon Qing Liu Yuan Liang | 2022/12/29 |
Signal receiving circuit, signal processing chip, communications device, and signal receiving method | 2021/9/21 |
