Chaochao Feng

National University of Defense Technology

H-index: 9

Asia-China

About Chaochao Feng

Chaochao Feng, With an exceptional h-index of 9 and a recent h-index of 7 (since 2020), a distinguished researcher at National University of Defense Technology, specializes in the field of Network-on-Chip, Computer Architecture, Microprocessor, VLSI Design.

His recent articles reflect a diverse array of research interests and contributions to the field:

LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing

Machine-learning-based multi-corner timing prediction for faster timing closure

Stage-based path delay prediction with customized machine learning technique

基于的特征选择的用于加速芯片物理设计 Floorplan 的机器学习框架

A machine learning framework with feature selection for floorplan acceleration in ic physical design

Chaochao Feng Information

University	National University of Defense Technology
Position	Assistant professor of Electronic Engineering
Citations(all)	764
Citations(since 2020)	273
Cited By	640
hIndex(all)	9
hIndex(since 2020)	7
i10Index(all)	9
i10Index(since 2020)	5
Email	Access Email
University Profile Page	National University of Defense Technology
Google Scholar	View Google Scholar Profile

Chaochao Feng Skills & Research Interests

Network-on-Chip

Computer Architecture

Microprocessor

VLSI Design

Top articles of Chaochao Feng

Title	Journal	Author(s)	Publication Date
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing		Yihong Hu Nuo Xu Chaochao Feng Wei Tong Kang Liu ...	2024/1/22
Machine-learning-based multi-corner timing prediction for faster timing closure	Electronics	Zhenyu Zhao Shuzheng Zhang Guoqiang Liu Chaochao Feng Tianhao Yang ...	2022/5/13
Stage-based path delay prediction with customized machine learning technique		Ao Han Zhenyu Zhao Chaochao Feng Shuzheng Zhang	2021/10/22
基于的特征选择的用于加速芯片物理设计 Floorplan 的机器学习框架	计算机科学技术学报	Shu-Zheng Zhang Zhen-Yu Zhao Chao-Chao Feng Lei Wang	2020/3/18
A machine learning framework with feature selection for floorplan acceleration in ic physical design	Journal of Computer Science and Technology	Shu-Zheng Zhang Zhen-Yu Zhao Chao-Chao Feng Lei Wang	2020/3