ProfessorsProfessors of National Institute of Technology, MeghalayaAnup Dandapat

Anup Dandapat

National Institute of Technology, Meghalaya

H-index: 15

Asia-India

About Anup Dandapat

Anup Dandapat, With an exceptional h-index of 15 and a recent h-index of 12 (since 2020), a distinguished researcher at National Institute of Technology, Meghalaya, specializes in the field of Low power VLSI.

His recent articles reflect a diverse array of research interests and contributions to the field:

A Low Power Partial Precharging based Double Tail Dynamic Comparator

Low Power Sense Amplifier For A 64× 32 Bit Sram Array For IOT Application

SMS-CAM: Shared matchline scheme for content addressable memory

Design of a 1.29–1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoM) for GPS and Satellite Navigation

A low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme

Analysis of the Universal Gates based on the Comparative Factors of Delay Propagation, Average Power Dissipation and Logical Effort

Modified Baugh Wooley Multiplier using Low Power Compressors

Match‐line control unit for power and delay reduction in hybrid CAM

Anup Dandapat Information

University	National Institute of Technology, Meghalaya
Position	___
Citations(all)	1131
Citations(since 2020)	590
Cited By	824
hIndex(all)	15
hIndex(since 2020)	12
i10Index(all)	24
i10Index(since 2020)	16
Email	Access Email
University Profile Page	National Institute of Technology, Meghalaya
Google Scholar	View Google Scholar Profile

Anup Dandapat Skills & Research Interests

Low power VLSI

Top articles of Anup Dandapat

Title	Journal	Author(s)	Publication Date
A Low Power Partial Precharging based Double Tail Dynamic Comparator	Authorea Preprints	Anup Dandapat Farhana Begum Md Najrul Islam Sandeep Mishra Kandarpa Kumar Sarma	2023/3/27
Low Power Sense Amplifier For A 64× 32 Bit Sram Array For IOT Application		Arundhati Dutta Gupta Shyamosree Goswami Anup Dandapat	2023/3/16
SMS-CAM: Shared matchline scheme for content addressable memory	Integration	Sheikh Wasmir Hussain Telajala Venkata Mahendra Sandeep Mishra Anup Dandapat	2023/1/1
Design of a 1.29–1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoM) for GPS and Satellite Navigation	Journal of Circuits, Systems and Computers	Keshab Das Anup Dandapat Sanjay Kumar Jana	2022/11/15
A low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme	Scientia Iranica	Farhana Begum Sandeep Mishra Anup Dandapat	2021/12/1
Analysis of the Universal Gates based on the Comparative Factors of Delay Propagation, Average Power Dissipation and Logical Effort		Vedanshu Kuwal Satyendra Singh Yadav Anup Dandapat	2021/5/21
Modified Baugh Wooley Multiplier using Low Power Compressors		Manolina Saha Anup Dandapat	2021/5/21
Match‐line control unit for power and delay reduction in hybrid CAM	IET Circuits, Devices & Systems	Sheikh Wasmir Hussain Telajala Venkata Mahendra Sandeep Mishra Anup Dandapat	2021/5
Low-power content addressable memory design using two-layer PN match-line control and sensing		Ya-Chun Lin Yen-Jen Chang Tung-Chi Wu	2013/8/4
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).	J. Inf. Sci. Eng.	Telajala Venkata Mahendra Sheikh Wasmir Hussain Sandeep Mishra Anup Dandapat	2020/9/1
Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory		Sheikh Wasmir Hussain Telajala Venkata Mahendra Sandeep Mishra Anup Dandapat	2020/6/5
The analogy of matchline sensing techniques for content addressable memory (CAM)		Sandeep Mishra Telajala Venkata Mahendra Sheikh Wasmir Hussain Anup Dandapat	2020/5
Energy-efficient precharge-free ternary content addressable memory (TCAM) for high search rate applications	IEEE Transactions on Circuits and Systems I: Regular Papers	Telajala Venkata Mahendra Sheikh Wasmir Hussain Sandeep Mishra Anup Dandapat	2020/3/11