Sudeendra kumar K

About Sudeendra kumar K

Sudeendra kumar K, With an exceptional h-index of 10 and a recent h-index of 8 (since 2020), a distinguished researcher at National Institute of Technology, Rourkela, specializes in the field of VLSI, DFT, Design for security.

His recent articles reflect a diverse array of research interests and contributions to the field:

Generation of Coverage based Verification Benchmark Programs for RISC-V Processor

Lightweight Secured Split Test Technique with RMA Capability to Prevent IC Counterfeiting

A Generic On-Board Computer based on RISC-V Architecture Processor for Low Cost Nanosatellite Applications

Improving Reliability of Embedded RISC-V SoC for Low-cost Space Applications

Sorter Design with Structured Low Power Techniques

PUF Based Authentication System for IoT Nodes: A Comparative Study

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

An Analysis of Stream and Block Ciphers for Scan Encryption

Sudeendra kumar K Information

University

Position

___

Citations(all)

286

Citations(since 2020)

221

Cited By

152

hIndex(all)

10

hIndex(since 2020)

8

i10Index(all)

10

i10Index(since 2020)

5

Email

University Profile Page

Google Scholar

Sudeendra kumar K Skills & Research Interests

VLSI

DFT

Design for security

Top articles of Sudeendra kumar K

Generation of Coverage based Verification Benchmark Programs for RISC-V Processor

2024/2/8

Lightweight Secured Split Test Technique with RMA Capability to Prevent IC Counterfeiting

2023/12/18

A Generic On-Board Computer based on RISC-V Architecture Processor for Low Cost Nanosatellite Applications

2023/5/5

Improving Reliability of Embedded RISC-V SoC for Low-cost Space Applications

2023/4/5

Sorter Design with Structured Low Power Techniques

SN Computer Science

2022/12/27

Sudeendra Kumar K
Sudeendra Kumar K

H-Index: 7

PUF Based Authentication System for IoT Nodes: A Comparative Study

2022/12/18

FPGA Design for Low Delay Comparison-free, Odd-even Merge Sorter

Indian Journal of Science and Technology

2022/5/12

An Analysis of Stream and Block Ciphers for Scan Encryption

2022/1/21

Low Power Sorters Using Clock Gating

2021/12/18

A Holistic Blockchain Based IC Traceability Technique

2021

Hardware Security: Hardware Trojan Detection, Test and Debug Security Infrastructure IP

2020

A novel reliable and aging tolerant modified RO PUF for low power application

Analog Integrated Circuits and Signal Processing

2020/6

See List of Professors in Sudeendra kumar K University(National Institute of Technology, Rourkela)

Co-Authors

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