Raffaele De Rose
Università della Calabria
H-index: 20
Europe-Italy
Top articles of Raffaele De Rose
PUF-Based Authentication-Oriented Architecture for Identification Tags
IEEE Transactions on Dependable and Secure Computing
2024/4/15
SIMPLY+: A Reliable STT-MRAM Based Smart Material Implication Architecture For In-Memory Computing
IEEE Access
2023/12/18
Experimental analysis of variability in WS2-based devices for hardware security
Solid-State Electronics
2023/9/1
Voltage-controlled magnetic anisotropy based physical unclonable function
Applied Physics Letters
2023/8/7
Raffaele De Rose
H-Index: 11
Giovanni Finocchio
H-Index: 28
Marco Lanuzza
H-Index: 17
Mario Carpentieri
H-Index: 24
Voltage reference with corner-aware replica selection/merging for 1.4-mV accuracy in harvested systems down to 3.9 pW, 0.2 V
IEEE Access
2023/1/5
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider
2022/10/24
Assessment of paper-based MoS2 FET for physically unclonable functions
Solid-State Electronics
2022/8/1
Smart material implication using spin-transfer torque magnetic tunnel junctions for logic-in-memory computing
Solid-State Electronics
2022/8/1
Adjusting thermal stability in double-barrier MTJ for energy improvement in cryogenic STT-MRAMs
Solid-State Electronics
2022/8/1
Static CMOS physically unclonable function based on 4T voltage divider with 0.6%–1.5% bit instability at 0.4–1.8 V operation in 180 nm
IEEE Journal of Solid-State Circuits
2022/8/1
Design of Ultra-Low Voltage/Power Circuits and Systems
2022/2/16
Marco Lanuzza
H-Index: 17
Raffaele De Rose
H-Index: 11
A 0.6-to-1.8 V CMOS current reference with near-100% power utilization
IEEE Transactions on Circuits and Systems II: Express Briefs
2021/6/3
Trimming-Less 0.2-V, 3.2-pW Voltage Reference Based on Corner-Aware Replica Combination with 1.6% Process Sensitivity, 1.4-mV Accuracy across PVT and Wafers
2021/6/2
Trimming-less voltage reference for highly uncertain harvesting down to 0.25 V, 5.4 pW
IEEE Journal of Solid-State Circuits
2021/5/28
Simulation analysis of DMTJ-based STT-MRAM operating at cryogenic temperatures
IEEE Transactions on Magnetics
2021/4/16
Raffaele De Rose
H-Index: 11
Felice Crupi
H-Index: 21
Mario Carpentieri
H-Index: 24
Adam Teman
H-Index: 19
Marco Lanuzza
H-Index: 17
Exploiting STT-MRAMs for cryogenic non-volatile cache applications
IEEE Transactions on Nanotechnology
2021/1/6
Assessment of 2d-fet based digital and analog circuits on paper
Solid-State Electronics
2021/11/1
Field-free magnetic tunnel junction for logic operations based on voltage-controlled magnetic anisotropy
IEEE Magnetics Letters
2021/10/8
Raffaele De Rose
H-Index: 11
Giovanni Finocchio
H-Index: 28
Marco Lanuzza
H-Index: 17
Mario Carpentieri
H-Index: 24
Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM
Solid-State Electronics
2021/10/1
STT-MTJ based smart implication for energy-efficient logic-in-memory computing
Solid-State Electronics
2021/10/1
Co-Authors
