Linyan Mei
Katholieke Universiteit Leuven
H-index: 8
Europe-Belgium
Top articles of Linyan Mei
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators
2023/11/6
Design Space Exploration of Deep Learning Accelerators
2023/8/24
Linyan Mei
H-Index: 3
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
2023/6/11
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators
2023/4/23
PetaOps/W edge-AI Processors: Myth or reality?
2023/4/17
Anteneh Gebregiorgis
H-Index: 7
Linyan Mei
H-Index: 3
Vikram Jain
H-Index: 1
Said Hamdioui
H-Index: 24
Marian Verhelst
H-Index: 25
Sander Stuijk
H-Index: 26
Sayandip De
H-Index: 6
Alexandra Jimborean
H-Index: 11
Luca Benini
H-Index: 62
Dimitrios Soudris
H-Index: 20
Ouassim Karrakchou
H-Index: 2
Tim Güneysu
H-Index: 33
Henk Corporaal
H-Index: 22
Defines: Enabling fast exploration of the depth-first scheduling space for dnn accelerators through analytical modeling
2023/2/25
Tinyvers: A tiny versatile system-on-chip with state-retentive eMRAM for ML inference at the extreme edge
IEEE Journal of Solid-State Circuits
2023/1/20
Towards heterogeneous multi-core accelerators exploiting fine-grained scheduling of layer-fused deep neural networks
arXiv preprint arXiv:2212.10612
2022/12/20
CONVOLVE: Smart and seamless design of smart edge processors
arXiv preprint arXiv:2212.00873
2022/12/1
Bandwidth-aware flexible-scheduling machine learning accelerator
2022/12/1
ML processors are going multi-core: A performance dream or a scheduling nightmare?
IEEE Solid-State Circuits Magazine
2022/11/15
Marian Verhelst
H-Index: 25
Linyan Mei
H-Index: 3
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, tiny versatile system-on-chip with state-retentive eMRAM for machine learning inference at the extreme edge
2022/6/12
A uniform latency model for DNN accelerators with diverse architectures and dataflows
2022/3/14
Taxonomy and benchmarking of precision-scalable MAC arrays under enhanced DNN dataflow representation
IEEE Transactions on Circuits and Systems I: Regular Papers
2022/1/14
Linyan Mei
H-Index: 3
Marian Verhelst
H-Index: 25
Hardware-efficient residual neural network execution in line-buffer depth-first processing
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
2021/10/14
Processor architecture optimization for spatially dynamic neural networks
2021/10/4
Analyzing the energy-latency-area-accuracy trade-off across contemporary neural networks
2021/6/6
LOMA: Fast auto-scheduling on DNN accelerators through loop-order-based memory allocation
2021/6/6
Linyan Mei
H-Index: 3
Marian Verhelst
H-Index: 25
ZigZag: Enlarging joint architecture-mapping design space exploration for DNN accelerators
IEEE Transactions on Computers
2021/2/22
Opportunities and limitations of emerging analog in-memory compute DNN architectures
2020/12/12
