Davide Rossi
Università degli Studi di Bologna
H-index: 36
Europe-Italy
Top articles of Davide Rossi
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
International Journal of Parallel Programming
2024/2/26
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation
IEEE Transactions on Circuits and Systems I: Regular Papers
2024/2/7
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
2023/4/17
Giuseppe Tagliavini
H-Index: 13
Alessandro Capotondi
H-Index: 8
Luca Benini
H-Index: 62
Davide Rossi
H-Index: 27
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes
2023/4/17
Seyed Ahmad Mirsalari
H-Index: 2
Giuseppe Tagliavini
H-Index: 13
Davide Rossi
H-Index: 27
Luca Benini
H-Index: 62
End-to-end DNN inference on a massively parallel analog in memory computing architecture
2023/4/17
Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode
IEEE Transactions on Circuits and Systems I: Regular Papers
2023/3/15
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2023/2/20
Jie Chen
H-Index: 32
Igor Loi
H-Index: 22
Giuseppe Tagliavini
H-Index: 13
Luca Benini
H-Index: 62
Davide Rossi
H-Index: 27
22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing
2023/2/19
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs
2023
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration
Future Generation Computer Systems
2023/12/1
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing
IEEE Journal of Solid-State Circuits
2023/10/3
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS
2023/9/11
Reducing Load-Use dependency-induced performance penalty in the Open-Source RISC-V CVA6 CPU
2023/9/6
Luca Benini
H-Index: 62
Davide Rossi
H-Index: 27
CVA6 RISC-V virtualization: Architecture, microarchitecture, and design space exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2023/8/28
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
2023/7/9
A 3 tops/w risc-v parallel cluster for inference of fine-grain mixed-precision quantized neural networks
2023/6/20
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays
2023/5/21
Cyber security aboard micro aerial vehicles: An opentitan-based visual communication use case
2023/5/21
Energy efficiency of opportunistic refreshing for Gain-Cell Embedded DRAM
IEEE Transactions on Circuits and Systems I: Regular Papers
2022/12/30
Darkside: A heterogeneous risc-v compute cluster for extreme-edge on-chip dnn inference and training
IEEE Open Journal of the Solid-State Circuits Society
2022/9/27
Co-Authors
